From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 19 Jun 2015 06:37:16 +0000 (+0200)
Subject: bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software... 
X-Git-Tag: 24jan2021_ls180~2099^2~46
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71627cf9f0d73f2992e7618fae0c7a7af25f8d6f;p=litex.git

bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)
---

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index 7e6224a7..a61f3aef 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -4,7 +4,6 @@ from migen.genlib.record import *
 from migen.genlib.misc import split, displacer, optree, chooser
 from migen.genlib.misc import FlipFlop, Counter
 from migen.genlib.fsm import FSM, NextState
-from migen.bank.description import *
 from migen.bus.transactions import *
 
 _layout = [
@@ -409,14 +408,13 @@ class Converter(Module):
             Record.connect(master, slave)
 
 
-class Cache(Module, AutoCSR):
+class Cache(Module):
     """Cache
 
     This module is a write-back wishbone cache that can be used as a L2 cache.
     Cachesize (in 32-bit words) is the size of the data store and must be a power of 2
     """
     def __init__(self, cachesize, master, slave):
-        self._size = CSRStatus(8, reset=log2_int(cachesize))
         self.master = master
         self.slave = slave