From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700)
Subject: split out instructions from openpower/isa/bitmanip.mdwn
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=717da5ae0c04672d7c271120d0986160f62ad63d;p=openpower-isa.git

split out instructions from openpower/isa/bitmanip.mdwn
---

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index 830962c9..d0603570 100644
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -2,154 +2,18 @@
 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
 <!-- These instructions are *not yet official* -->
 
-# Ternary Bitwise Logic Immediate
+[[!inline pagenames="openpower/isa/bitmanip/ternlogi" raw="yes"]]
 
-TLI-Form
+[[!inline pagenames="openpower/isa/bitmanip/grev" raw="yes"]]
 
-* ternlogi RT,RA,RB,TLI (Rc=0)
-* ternlogi. RT,RA,RB,TLI (Rc=1)
+[[!inline pagenames="openpower/isa/bitmanip/grevi" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/bitmanip/grevw" raw="yes"]]
 
-    result <- [0] * XLEN
-    do i = 0 to XLEN - 1
-      idx <- (RT)[i] || (RA)[i] || (RB)[i]
-      result[i] <- TLI[7-idx]
-    RT <- result
+[[!inline pagenames="openpower/isa/bitmanip/grevwi" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/bitmanip/sadd" raw="yes"]]
 
-    CR0                    (if Rc=1)
+[[!inline pagenames="openpower/isa/bitmanip/saddw" raw="yes"]]
 
-# Generalized Bit-Reverse
-
-X-Form
-
-* grev RT,RA,RB (Rc=0)
-* grev. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * XLEN
-    b <- EXTZ64(RB)
-    do i = 0 to XLEN - 1
-      idx <- b[64-log2(XLEN):63] ^ i
-      result[i] <- (RA)[idx]
-    RT <- result
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Generalized Bit-Reverse Immediate
-
-XB-Form
-
-* grevi RT,RA,XBI (Rc=0)
-* grevi. RT,RA,XBI (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * XLEN
-    do i = 0 to XLEN - 1
-      idx <- XBI[6-log2(XLEN):5] ^ i
-      result[i] <- (RA)[idx]
-    RT <- result
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Generalized Bit-Reverse Word
-
-X-Form
-
-* grevw RT,RA,RB (Rc=0)
-* grevw. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * (XLEN / 2)
-    a <- (RA)[XLEN/2:XLEN-1]
-    b <- EXTZ64(RB)
-    do i = 0 to XLEN / 2 - 1
-      idx <- b[64-log2(XLEN/2):63] ^ i
-      result[i] <- a[idx]
-    RT <- ([0] * (XLEN / 2)) || result
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Generalized Bit-Reverse Word Immediate
-
-X-Form
-
-* grevwi RT,RA,SH (Rc=0)
-* grevwi. RT,RA,SH (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * (XLEN / 2)
-    a <- (RA)[XLEN/2:XLEN-1]
-    do i = 0 to XLEN / 2 - 1
-      idx <- SH[5-log2(XLEN/2):4] ^ i
-      result[i] <- a[idx]
-    RT <- ([0] * (XLEN / 2)) || result
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Add With Shift By Immediate
-
-Z23-Form
-
-* sadd RT,RA,RB,SH (Rc=0)
-* sadd. RT,RA,RB,SH (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)
-    m <- ((0b0 || SH) + 1)
-    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Add With Shift By Immediate Word
-
-Z23-Form
-
-* saddw RT,RA,RB,SH (Rc=0)
-* saddw. RT,RA,RB,SH (Rc=1)
-
-Pseudo-code:
-
-    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
-    if (RB)[XLEN/2] = 1 then
-        n[0:XLEN/2-1] <- [1]*(XLEN/2)
-    m <- ((0b0 || SH) + 1)
-    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Add With Shift By Immediate Unsigned Word
-
-Z23-Form
-
-* sadduw RT,RA,RB,SH (Rc=0)
-* sadduw. RT,RA,RB,SH (Rc=1)
-
-Pseudo-code:
-
-    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
-    m <- ((0b0 || SH) + 1)
-    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
+[[!inline pagenames="openpower/isa/bitmanip/sadduw" raw="yes"]]
diff --git a/openpower/isa/bitmanip/grev.mdwn b/openpower/isa/bitmanip/grev.mdwn
new file mode 100644
index 00000000..2e7e9cfa
--- /dev/null
+++ b/openpower/isa/bitmanip/grev.mdwn
@@ -0,0 +1,14 @@
+# Generalized Bit-Reverse
+
+X-Form
+
+* grev RT,RA,RB (Rc=0)
+* grev. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/grev_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/grev_code.mdwn b/openpower/isa/bitmanip/grev_code.mdwn
new file mode 100644
index 00000000..442196fe
--- /dev/null
+++ b/openpower/isa/bitmanip/grev_code.mdwn
@@ -0,0 +1,6 @@
+    result <- [0] * XLEN
+    b <- EXTZ64(RB)
+    do i = 0 to XLEN - 1
+      idx <- b[64-log2(XLEN):63] ^ i
+      result[i] <- (RA)[idx]
+    RT <- result
diff --git a/openpower/isa/bitmanip/grevi.mdwn b/openpower/isa/bitmanip/grevi.mdwn
new file mode 100644
index 00000000..d5ab2b7a
--- /dev/null
+++ b/openpower/isa/bitmanip/grevi.mdwn
@@ -0,0 +1,14 @@
+# Generalized Bit-Reverse Immediate
+
+XB-Form
+
+* grevi RT,RA,XBI (Rc=0)
+* grevi. RT,RA,XBI (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/grevi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/grevi_code.mdwn b/openpower/isa/bitmanip/grevi_code.mdwn
new file mode 100644
index 00000000..9d5f41fe
--- /dev/null
+++ b/openpower/isa/bitmanip/grevi_code.mdwn
@@ -0,0 +1,5 @@
+    result <- [0] * XLEN
+    do i = 0 to XLEN - 1
+      idx <- XBI[6-log2(XLEN):5] ^ i
+      result[i] <- (RA)[idx]
+    RT <- result
diff --git a/openpower/isa/bitmanip/grevw.mdwn b/openpower/isa/bitmanip/grevw.mdwn
new file mode 100644
index 00000000..2b989499
--- /dev/null
+++ b/openpower/isa/bitmanip/grevw.mdwn
@@ -0,0 +1,14 @@
+# Generalized Bit-Reverse Word
+
+X-Form
+
+* grevw RT,RA,RB (Rc=0)
+* grevw. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/grevw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/grevw_code.mdwn b/openpower/isa/bitmanip/grevw_code.mdwn
new file mode 100644
index 00000000..1f7355ab
--- /dev/null
+++ b/openpower/isa/bitmanip/grevw_code.mdwn
@@ -0,0 +1,7 @@
+    result <- [0] * (XLEN / 2)
+    a <- (RA)[XLEN/2:XLEN-1]
+    b <- EXTZ64(RB)
+    do i = 0 to XLEN / 2 - 1
+      idx <- b[64-log2(XLEN/2):63] ^ i
+      result[i] <- a[idx]
+    RT <- ([0] * (XLEN / 2)) || result
diff --git a/openpower/isa/bitmanip/grevwi.mdwn b/openpower/isa/bitmanip/grevwi.mdwn
new file mode 100644
index 00000000..2daf225f
--- /dev/null
+++ b/openpower/isa/bitmanip/grevwi.mdwn
@@ -0,0 +1,14 @@
+# Generalized Bit-Reverse Word Immediate
+
+X-Form
+
+* grevwi RT,RA,SH (Rc=0)
+* grevwi. RT,RA,SH (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/grevwi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/grevwi_code.mdwn b/openpower/isa/bitmanip/grevwi_code.mdwn
new file mode 100644
index 00000000..fc1fbbc0
--- /dev/null
+++ b/openpower/isa/bitmanip/grevwi_code.mdwn
@@ -0,0 +1,6 @@
+    result <- [0] * (XLEN / 2)
+    a <- (RA)[XLEN/2:XLEN-1]
+    do i = 0 to XLEN / 2 - 1
+      idx <- SH[5-log2(XLEN/2):4] ^ i
+      result[i] <- a[idx]
+    RT <- ([0] * (XLEN / 2)) || result
diff --git a/openpower/isa/bitmanip/sadd.mdwn b/openpower/isa/bitmanip/sadd.mdwn
new file mode 100644
index 00000000..d09346e7
--- /dev/null
+++ b/openpower/isa/bitmanip/sadd.mdwn
@@ -0,0 +1,14 @@
+# Add With Shift By Immediate
+
+Z23-Form
+
+* sadd RT,RA,RB,SH (Rc=0)
+* sadd. RT,RA,RB,SH (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/sadd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/sadd_code.mdwn b/openpower/isa/bitmanip/sadd_code.mdwn
new file mode 100644
index 00000000..1688d90d
--- /dev/null
+++ b/openpower/isa/bitmanip/sadd_code.mdwn
@@ -0,0 +1,3 @@
+    n <- (RB)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
diff --git a/openpower/isa/bitmanip/sadduw.mdwn b/openpower/isa/bitmanip/sadduw.mdwn
new file mode 100644
index 00000000..3281ca9a
--- /dev/null
+++ b/openpower/isa/bitmanip/sadduw.mdwn
@@ -0,0 +1,14 @@
+# Add With Shift By Immediate Unsigned Word
+
+Z23-Form
+
+* sadduw RT,RA,RB,SH (Rc=0)
+* sadduw. RT,RA,RB,SH (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/sadduw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/sadduw_code.mdwn b/openpower/isa/bitmanip/sadduw_code.mdwn
new file mode 100644
index 00000000..f5e1b95d
--- /dev/null
+++ b/openpower/isa/bitmanip/sadduw_code.mdwn
@@ -0,0 +1,3 @@
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
diff --git a/openpower/isa/bitmanip/saddw.mdwn b/openpower/isa/bitmanip/saddw.mdwn
new file mode 100644
index 00000000..dbb5edf6
--- /dev/null
+++ b/openpower/isa/bitmanip/saddw.mdwn
@@ -0,0 +1,14 @@
+# Add With Shift By Immediate Word
+
+Z23-Form
+
+* saddw RT,RA,RB,SH (Rc=0)
+* saddw. RT,RA,RB,SH (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/saddw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/saddw_code.mdwn b/openpower/isa/bitmanip/saddw_code.mdwn
new file mode 100644
index 00000000..dfae8752
--- /dev/null
+++ b/openpower/isa/bitmanip/saddw_code.mdwn
@@ -0,0 +1,5 @@
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    if (RB)[XLEN/2] = 1 then
+        n[0:XLEN/2-1] <- [1]*(XLEN/2)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
diff --git a/openpower/isa/bitmanip/ternlogi.mdwn b/openpower/isa/bitmanip/ternlogi.mdwn
new file mode 100644
index 00000000..ecbd2227
--- /dev/null
+++ b/openpower/isa/bitmanip/ternlogi.mdwn
@@ -0,0 +1,14 @@
+# Ternary Bitwise Logic Immediate
+
+TLI-Form
+
+* ternlogi RT,RA,RB,TLI (Rc=0)
+* ternlogi. RT,RA,RB,TLI (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/bitmanip/ternlogi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/bitmanip/ternlogi_code.mdwn b/openpower/isa/bitmanip/ternlogi_code.mdwn
new file mode 100644
index 00000000..7f441fb2
--- /dev/null
+++ b/openpower/isa/bitmanip/ternlogi_code.mdwn
@@ -0,0 +1,5 @@
+    result <- [0] * XLEN
+    do i = 0 to XLEN - 1
+      idx <- (RT)[i] || (RA)[i] || (RB)[i]
+      result[i] <- TLI[7-idx]
+    RT <- result