From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 6 Feb 2015 12:03:38 +0000 (+0100)
Subject: platforms/kc705: add more clock constraints
X-Git-Tag: 24jan2021_ls180~2604^2~68
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7180b5273c5c3389a1d7b2844c01e44e8d5f0f18;p=litex.git

platforms/kc705: add more clock constraints
---

diff --git a/platforms/kc705.py b/platforms/kc705.py
index a0e2098f..500d1b07 100644
--- a/platforms/kc705.py
+++ b/platforms/kc705.py
@@ -121,4 +121,18 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
 				self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
 			except ConstraintError:
 				pass
+			self.add_platform_command("""
+create_clock -name sys_clk -period 6 [get_nets sys_clk]
+create_clock -name eth_rx_clk -period 8 [get_nets eth_rx_clk]
+create_clock -name eth_tx_clk -period 8 [get_nets eth_tx_clk]
+
+set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
+set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
+set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
+set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 2.5 [current_design]
+""")
+
 	return RealPlatform(*args, **kwargs)
diff --git a/test/test_regs.py b/test/test_regs.py
index 982f849c..ffb018f3 100644
--- a/test/test_regs.py
+++ b/test/test_regs.py
@@ -3,6 +3,7 @@ from config import *
 wb.open()
 regs = wb.regs
 ###
+regs.ethphy_crg_reset.write(1)
 print("sysid     : 0x%04x" %regs.identifier_sysid.read())
 print("revision  : 0x%04x" %regs.identifier_revision.read())
 print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
diff --git a/test/test_udpip.py b/test/test_udpip.py
index a33fa320..eb980c99 100644
--- a/test/test_udpip.py
+++ b/test/test_udpip.py
@@ -24,7 +24,7 @@ regs.bist_generator_length.write(64)
 
 conditions = {}
 conditions = {
-	"udpip_core_mac_tx_cdc_sink_stb"	: 1
+	"udpipsocdevel_mac_tx_cdc_sink_stb"	: 1
 }
 la.configure_term(port=0, cond=conditions)
 la.configure_sum("term")