From: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu, 17 Apr 2014 03:15:23 +0000 (-0700)
Subject: i965: Retype pre-Gen6 varying pull load destination to UW.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71846a943f9b699d0f234d919dcb8d1934943693;p=mesa.git

i965: Retype pre-Gen6 varying pull load destination to UW.

This sets up the proper execution mask for sends in SIMD16 mode.

Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2,
glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake,
which regressed when I enabled SIMD16 pull parameter support in
commit b207e88b25e526d0f1ada7b19605b880a27866dc.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index c6b4aae4087..ff85171bb61 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -912,7 +912,7 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
 
    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
    send->header.compression_control = BRW_COMPRESSION_NONE;
-   brw_set_dest(p, send, dst);
+   brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
    brw_set_src0(p, send, header);
    if (brw->gen < 6)
       send->header.destreg__conditionalmod = inst->base_mrf;