From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 27 Oct 2020 20:33:38 +0000 (+0000)
Subject: further investigation note
X-Git-Tag: convert-csv-opcode-to-binary~1912
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71a02c6a4c8f12d2a08074e963ec4e1270433a79;p=libreriscv.git

further investigation note
---

diff --git a/3d_gpu/architecture/compared_to_register_renaming.mdwn b/3d_gpu/architecture/compared_to_register_renaming.mdwn
index 8b4e2e4c7..15430a7f9 100644
--- a/3d_gpu/architecture/compared_to_register_renaming.mdwn
+++ b/3d_gpu/architecture/compared_to_register_renaming.mdwn
@@ -12,7 +12,8 @@ are spread out across multiple physical registers.
 stations.  unlike in the Tomasulo Algorithm, they're just not given
 "names" because Cray and Thornton solved a problem they didn't realise
 everyone else would have.  See [[tomasulo_transformation]] and
-<http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/001050.html>)
+<http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/001050.html>
+However further investigation shows that this may be WaW hazard relate)
 
 The following diagrams are assuming that the fetch, decode, branch
 prediction, and register renaming can handle 4 instructions per clock