From: lkcl <lkcl@web>
Date: Sat, 23 Jan 2021 21:15:45 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~372
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71b7bc3be4e2dc889c0346b08c6b18fad4fcbab1;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 8df72f367..7c1ffbaa5 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -644,6 +644,21 @@ For actual assembler:
 
     sv.asmcode/mode.vec{N}.ew=8,sw=16,m={pred},sm={pred} reg.v, src.s
 
+Qualifiers:
+
+* vec{N}: vec2 OR vec3 OR vec4 - sets SUBVL=2/3/4
+* ew={N}: ew=8/16/32 - sets elwidth override
+* sw={N}: sw=8/16/32 - sets source elwidth override
+* ff={xx}: see fail-first mode
+* pr={xx}: see predicate-result mode
+* sat{x}: satu / sats - see saturation mode
+* mr: see map-reduce mode
+* mr.svm see map-reduce with sub-vector mode
+* crm: see map-reduce CR mode
+* crm.svm see map-reduce CR with sub-vector mode
+* sz: predication with source-zeroing
+* dz: predication with dest-zeroing
+
 For modes:
 
 * pred-result:
@@ -658,3 +673,4 @@ For modes:
 * map-reduce:
   - mr OR crm: "normal" map-reduce mode or CR-mode
   - svm: when SUBVL=2/3/4 (vec2/3/4) sub-vector mapreduce is enabled
+