From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 30 Jun 2013 12:32:47 +0000 (+0200)
Subject: fhdl/verilog: lower complex slices before reset insertion
X-Git-Tag: 24jan2021_ls180~2099^2~541
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71b89e4c46e5487e995f6de6f2d1cb478479264c;p=litex.git

fhdl/verilog: lower complex slices before reset insertion
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index d9683e94..7a6f7ce6 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -302,6 +302,7 @@ def convert(f, ios=None, name="top",
 			else:
 				raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 	
+	f = lower_complex_slices(f)
 	_insert_resets(f)
 	f = lower_basics(f)
 	fs, lowered_specials = _lower_specials(special_overrides, f.specials)