From: Jacob Lifshay Date: Tue, 16 May 2023 06:53:40 +0000 (-0700) Subject: fcvttg*: test FPSCR output X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71ba100da2dbb08037e0e6caae4989d4977d24b2;p=openpower-isa.git fcvttg*: test FPSCR output --- diff --git a/src/openpower/test/fmv_fcvt/fmv_fcvt.py b/src/openpower/test/fmv_fcvt/fmv_fcvt.py index 51de74af..6759bb6a 100644 --- a/src/openpower/test/fmv_fcvt/fmv_fcvt.py +++ b/src/openpower/test/fmv_fcvt/fmv_fcvt.py @@ -3,14 +3,16 @@ from openpower.sv.trans.svp64 import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State +from openpower.fpscr import FPSCRState import struct import math class FMvFCvtCases(TestAccumulatorBase): - def js_toint32(self, inp, expected, test_title=""): + def js_toint32(self, inp, expected, test_title="", inp_bits=None): inp = float(inp) - inp_bits = struct.unpack("