From: Christoph Bumiller <e0425955@student.tuwien.ac.at>
Date: Sat, 6 Apr 2013 15:40:02 +0000 (+0200)
Subject: nvc0: patch up TEX cases with 5 or 6 sources on nve4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71c1c8a9b89ca1ecca1857c53cd8c648c9c9a871;p=mesa.git

nvc0: patch up TEX cases with 5 or 6 sources on nve4

Hackishly fixes alignment requirement of 2nd tuple for now.
---

diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
index 5f0f2e72231..c459d60759b 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
@@ -728,13 +728,31 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
    if (i->tex.useOffsets) {
       uint32_t value = 0;
       int n, c;
-      int s = i->srcCount(0xff);
+      int s = i->srcCount(0xff, true);
+      if (i->srcExists(s)) // move potential predicate out of the way
+         i->moveSources(s, 1);
       for (n = 0; n < i->tex.useOffsets; ++n)
          for (c = 0; c < 3; ++c)
             value |= (i->tex.offset[n][c] & 0xf) << (n * 12 + c * 4);
       i->setSrc(s, bld.loadImm(NULL, value));
    }
 
+   if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) {
+      //
+      // If TEX requires more than 4 sources, the 2nd register tuple must be
+      // aligned to 4, even if it consists of just a single 4-byte register.
+      //
+      // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
+      //
+      int s = i->srcCount(0xff, true);
+      if (s > 4 && s < 7) {
+         if (i->srcExists(s)) // move potential predicate out of the way
+            i->moveSources(s, 7 - s);
+         while (s < 7)
+            i->setSrc(s++, bld.loadImm(NULL, 0));
+      }
+   }
+
    return true;
 }