From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 7 Nov 2011 09:13:43 +0000 (-0800)
Subject: SE/FS: Get rid of FULL_SYSTEM in mem.
X-Git-Tag: stable_2012_06_28~287
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71c4534ce96b8b663a1f35ee98dd19c0438f5fde;p=gem5.git

SE/FS: Get rid of FULL_SYSTEM in mem.
---

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 7863edde0..09e3d0869 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -38,6 +38,7 @@
 #include "debug/Cache.hh"
 #include "mem/cache/base.hh"
 #include "mem/cache/mshr.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -151,11 +152,7 @@ BaseCache::regStats()
         const string &cstr = cmd.toString();
 
         hits[access_idx]
-#if FULL_SYSTEM
-            .init(_numCpus + 1)
-#else
-            .init(_numCpus)
-#endif
+            .init(FullSystem ? (_numCpus + 1) : _numCpus)
             .name(name() + "." + cstr + "_hits")
             .desc("number of " + cstr + " hits")
             .flags(total | nozero | nonan)
@@ -192,11 +189,7 @@ BaseCache::regStats()
         const string &cstr = cmd.toString();
 
         misses[access_idx]
-#if FULL_SYSTEM
-            .init(_numCpus + 1)
-#else
-            .init(_numCpus)
-#endif
+            .init(FullSystem ? (_numCpus + 1) : _numCpus)
             .name(name() + "." + cstr + "_misses")
             .desc("number of " + cstr + " misses")
             .flags(total | nozero | nonan)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 297692b32..eaab2494e 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -57,6 +57,7 @@
 #include "mem/tport.hh"
 #include "params/BaseCache.hh"
 #include "sim/eventq.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_exit.hh"
 
 class MSHR;
@@ -505,12 +506,10 @@ class BaseCache : public MemObject
              * available, meanwhile writeback hit/miss stats are not used
              * in any aggregate hit/miss calculations, so just lump them all
              * in bucket 0 */
-#if FULL_SYSTEM
-        } else if (id == -1) {
+        } else if (FullSystem && id == -1) {
             // Device accesses have id -1
             // lump device accesses into their own bucket
             misses[pkt->cmdToIndex()][_numCpus]++;
-#endif
         } else {
             misses[pkt->cmdToIndex()][id % _numCpus]++;
         }
@@ -533,12 +532,10 @@ class BaseCache : public MemObject
         if (pkt->cmd == MemCmd::Writeback) {
             assert(id == -1);
             hits[pkt->cmdToIndex()][0]++;
-#if FULL_SYSTEM
-        } else if (id == -1) {
+        } else if (FullSystem && id == -1) {
             // Device accesses have id -1
             // lump device accesses into their own bucket
             hits[pkt->cmdToIndex()][_numCpus]++;
-#endif
         } else {
             /* the % is necessary in case there are switch cpus */
             hits[pkt->cmdToIndex()][id % _numCpus]++;