From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Feb 2020 11:56:12 +0000 (+0000)
Subject: add sim just to see if anything happens
X-Git-Tag: partial-core-ls180-gdsii~218
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71c8a857c2cea5ea7f63b8739791f326a86122c1;p=soclayout.git

add sim just to see if anything happens
---

diff --git a/experiments/Makefile b/experiments/Makefile
index 2a56df5..e4cb645 100755
--- a/experiments/Makefile
+++ b/experiments/Makefile
@@ -10,6 +10,7 @@
                  USE_KITE = No
 
                  NETLISTS = $(shell cat nets.txt)
+                 PATTERNS = alu_hier_r
 
 
  include ./mk/design-flow.mk
@@ -23,3 +24,4 @@ gds:       alu_hier_cts_r.gds
 lvx:       lvx-alu_hier_cts_r
 druc:      druc-alu_hier_cts_r
 view:      cgt-alu_hier_cts_r
+sim:       asimut-alu_hier_cts_r