From: Luke Kenneth Casson Leighton Date: Mon, 5 Sep 2022 16:23:12 +0000 (+0100) Subject: remove parallel-reduction mode from decoder and sv/trans/svp64.py X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71d43fc101d84940ff3e91dea87cbd6e68e60d6e;p=openpower-isa.git remove parallel-reduction mode from decoder and sv/trans/svp64.py parallel reduction has to be done through REMAP due to two critical factors: 1) the amount of gates in joining REMAP with PREDUCE as a "Mode" 2) the differing Vector Length (similar to Matrix) from the number of operations needed to be performed the complexity arising is too great which means it has to be done as REMAP --- diff --git a/src/openpower/consts.py b/src/openpower/consts.py index d1e7f626..65f2bc08 100644 --- a/src/openpower/consts.py +++ b/src/openpower/consts.py @@ -241,6 +241,7 @@ class SVP64MODEb(_Const): # mode bits MOD2_MSB = 0 MOD2_LSB = 1 + MOD3 = 3 # pack detection (TODO, CR-ops needs one of these too) LDST_PACK = 2 # set =1 for LD/ST-immediate Pack mode ARITH_PACK = 4 # set =1 for Arithmetic Pack mode @@ -254,7 +255,6 @@ class SVP64MODEb(_Const): BC_CTRTEST = 0 # CTR-test mode # reduce mode REDUCE = 2 # 0=normal predication 1=reduce mode - PTREDUCE = 3 # 1=parallel reduce, 0=scalar reduce SVM = 3 # subvector reduce mode 0=independent 1=horizontal CRM = 4 # CR mode on reduce (Rc=1) 0=some 1=all RG = 4 # Reverse-gear on reduce diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index c02fa6ea..29faffb1 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -297,7 +297,6 @@ class SVP64RMMode(Enum): SATURATE = 3 PREDRES = 4 BRANCH = 5 - PTREDUCE = 6 # Parallel Reduction @unique diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py index a28d612c..85492ddb 100644 --- a/src/openpower/decoder/power_svp64_rm.py +++ b/src/openpower/decoder/power_svp64_rm.py @@ -70,7 +70,6 @@ Arithmetic: | --- | --- |---------|-------------------------- | | 00 | 0 | dz sz | simple mode | | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | -| 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | | 00 | 1 | SVM 0 | subvector reduce mode, SUBVL>1 | | 00 | 1 | SVM 1 | Pack/Unpack mode, SUBVL>1 | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | @@ -180,13 +179,10 @@ class SVP64RMModeDecode(Elaboratable): comb += self.mode.eq(SVP64RMMode.NORMAL) comb += do_pu.eq(mode[SVP64MODE.LDST_PACK]) # Pack mode with m.Elif(mode[SVP64MODE.REDUCE]): - with m.If(mode[SVP64MODE.PTREDUCE]): - comb += self.mode.eq(SVP64RMMode.PTREDUCE) - with m.Else(): - comb += self.mode.eq(SVP64RMMode.MAPREDUCE) - # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1 - with m.If(self.rm_in.subvl != Const(0, 2)): # active - comb += do_pu.eq(mode[SVP64MODE.ARITH_PACK]) + comb += self.mode.eq(SVP64RMMode.MAPREDUCE) + # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1 + with m.If(self.rm_in.subvl != Const(0, 2)): # active + comb += do_pu.eq(mode[SVP64MODE.ARITH_PACK]) with m.Else(): comb += self.mode.eq(SVP64RMMode.NORMAL) with m.Case(1): @@ -200,7 +196,7 @@ class SVP64RMModeDecode(Elaboratable): with m.If((~is_ldst) & # not for LD/ST (mode2 == 0) & # first 2 bits == 0 mode[SVP64MODE.REDUCE] & # bit 2 == 1 - (~mode[SVP64MODE.PTREDUCE])): # not parallel mapreduce + (~mode[SVP64MODE.MOD3])): # bit 3 == 0 comb += self.reverse_gear.eq(mode[SVP64MODE.RG]) # finally whew # extract zeroing diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 15844a26..6d703cc4 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -982,7 +982,6 @@ class SVP64Asm: dst_zero = 0 sv_mode = None - parallel = False mapreduce = False reverse_gear = False mapreduce_crm = False @@ -1069,11 +1068,6 @@ class SVP64Asm: assert sv_mode is None sv_mode = 0b00 mapreduce = True - # parallel prefix mode - elif encmode == 'pp': - assert sv_mode is None - sv_mode = 0b00 - parallel = True elif encmode == 'crm': # CR on map-reduce assert sv_mode is None sv_mode = 0b00 @@ -1163,7 +1157,6 @@ class SVP64Asm: | --- | --- |---------|-------------------------- | | 00 | 0 | dz sz | simple mode | | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | - | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | | 00 | 1 | SVM 0 | subvector reduce mode, SUBVL>1 | | 00 | 1 | SVM 1 | Pack/Unpack mode, SUBVL>1 | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | @@ -1234,11 +1227,7 @@ class SVP64Asm: ###################################### # "mapreduce" modes elif sv_mode == 0b00: - if parallel: - mode |= (0b1 << SVP64MODE.PTREDUCE) # sets parallel reduce - assert subvl == 0, "TODO sub-vector parallel reduce" - else: - mode |= (0b1 << SVP64MODE.REDUCE) # sets mapreduce + mode |= (0b1 << SVP64MODE.REDUCE) # sets mapreduce assert dst_zero == 0, "dest-zero not allowed in mapreduce mode" if reverse_gear: mode |= (0b1 << SVP64MODE.RG) # sets Reverse-gear mode @@ -1596,9 +1585,6 @@ if __name__ == '__main__': 'sv.ffmadds 6.v, 2.v, 4.v, 6.v', # correctly converted to .long 'svshape2 8, 1, 31, 7, 1, 1', ] - lst = [ - 'sv.add./pp 5.v, 2.v, 1.v', - ] isa = SVP64Asm(lst, macros=macros) log("list:\n", "\n\t".join(list(isa))) # running svp64.py is designed to test hard-coded lists