From: Steve Reinhardt Date: Mon, 22 Sep 2014 03:04:39 +0000 (-0400) Subject: stats: update t1000 stats for recent changes X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71d5f03175b3a684b94bbc515ebc02e2b493b7cf;p=gem5.git stats: update t1000 stats for recent changes --- diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index f59a11c09..ccf2bc154 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -16,10 +16,10 @@ cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 hypervisor_addr=1099243257856 -hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin +hypervisor_bin=/dist/m5/system/binaries/q_new.bin hypervisor_desc=system.hypervisor_desc hypervisor_desc_addr=133446500352 -hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin +hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin init_param=0 kernel= kernel_addr_check=true @@ -27,19 +27,19 @@ load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic mem_ranges=1048576:68157439 2147483648:2415919103 -memories=system.partition_desc system.rom system.nvram system.physmem1 system.hypervisor_desc system.physmem0 +memories=system.hypervisor_desc system.physmem1 system.partition_desc system.physmem0 system.rom system.nvram num_work_ids=16 nvram=system.nvram nvram_addr=133429198848 -nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1 +nvram_bin=/dist/m5/system/binaries/nvram1 openboot_addr=1099243716608 -openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin +openboot_bin=/dist/m5/system/binaries/openboot_new.bin partition_desc=system.partition_desc partition_desc_addr=133445976064 -partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +partition_desc_bin=/dist/m5/system/binaries/1up-md.bin +readfile=/z/stever/hg/gem5/tests/halt.sh reset_addr=1099243192320 -reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin +reset_bin=/dist/m5/system/binaries/reset_new.bin rom=system.rom symbolfile= work_begin_ckpt_count=0 @@ -95,9 +95,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -163,7 +160,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2 +image_file=/dist/m5/system/disks/disk.s10hw2 read_only=true [system.dvfs_handler] @@ -193,7 +190,7 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 @@ -203,11 +200,12 @@ master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake slave=system.bridge.master [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json index e4d168593..300aaf6af 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json @@ -2,30 +2,16 @@ "name": null, "sim_quantum": 0, "system": { - "bridge": { - "slave": { - "peer": "system.membus.master[2]", - "role": "SLAVE" - }, - "name": "bridge", - "req_size": 16, - "delay": 5.0000000000000004e-08, - "eventq_index": 0, - "master": { - "peer": "system.iobus.slave[0]", - "role": "MASTER" - }, - "cxx_class": "Bridge", - "path": "system.bridge", - "resp_size": 16, - "type": "Bridge" - }, + "kernel": "", "kernel_addr_check": true, "rom": { - "latency": 3.0000000000000004e-08, + "range": "1099243192320:1099251580927", + "latency": 60, "name": "rom", "eventq_index": 0, - "latency_var": 0.0, + "clk_domain": "system.clk_domain", + "latency_var": 0, + "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", "path": "system.rom", @@ -37,62 +23,31 @@ }, "in_addr_map": true }, - "membus": { + "bridge": { + "ranges": [ + "133412421632:133412421639", + "134217728000:554050781183", + "644245094400:652835028991", + "725849473024:1095485095935", + "1099255955456:1099255955463" + ], "slave": { - "peer": [ - "system.system_port", - "system.cpu.icache_port", - "system.cpu.dcache_port" - ], + "peer": "system.membus.master[2]", "role": "SLAVE" }, - "name": "membus", - "badaddr_responder": { - "ret_data8": 255, - "name": "badaddr_responder", - "pio": { - "peer": "system.membus.default", - "role": "SLAVE" - }, - "ret_bad_addr": true, - "pio_latency": 1.0000000000000001e-07, - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, - "ret_data64": 18446744073709551615, - "cxx_class": "IsaFake", - "path": "system.membus.badaddr_responder", - "pio_addr": 0, - "type": "IsaFake", - "ret_data16": 65535 - }, - "default": { - "peer": "system.membus.badaddr_responder.pio", - "role": "MASTER" - }, - "header_cycles": 1, - "width": 8, + "name": "bridge", + "req_size": 16, + "clk_domain": "system.clk_domain", + "delay": 100, "eventq_index": 0, "master": { - "peer": [ - "system.t1000.iob.pio", - "system.t1000.htod.pio", - "system.bridge.slave", - "system.rom.port", - "system.nvram.port", - "system.hypervisor_desc.port", - "system.partition_desc.port", - "system.physmem0.port", - "system.physmem1.port" - ], + "peer": "system.iobus.slave[0]", "role": "MASTER" }, - "cxx_class": "CoherentBus", - "path": "system.membus", - "type": "CoherentBus", - "use_default_range": false + "cxx_class": "Bridge", + "path": "system.bridge", + "resp_size": 16, + "type": "Bridge" }, "iobus": { "slave": { @@ -102,6 +57,7 @@ "role": "SLAVE" }, "name": "iobus", + "clk_domain": "system.clk_domain", "header_cycles": 1, "width": 8, "eventq_index": 0, @@ -125,9 +81,9 @@ ], "role": "MASTER" }, - "cxx_class": "NoncoherentBus", + "cxx_class": "NoncoherentXBar", "path": "system.iobus", - "type": "NoncoherentBus", + "type": "NoncoherentXBar", "use_default_range": false }, "t1000": { @@ -138,7 +94,9 @@ "role": "SLAVE" }, "time": "Thu Jan 1 00:00:00 2009", - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", + "system": "system", "eventq_index": 0, "cxx_class": "DumbTOD", "path": "system.t1000.htod", @@ -151,7 +109,11 @@ "peer": "system.iobus.master[12]", "role": "SLAVE" }, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", + "system": "system", + "terminal": "system.t1000.pterm", + "platform": "system.t1000", "eventq_index": 0, "cxx_class": "Uart8250", "path": "system.t1000.puart0", @@ -159,14 +121,17 @@ "type": "Uart8250" }, "fake_membnks": { + "system": "system", "ret_data8": 255, "name": "fake_membnks", + "warn_access": "", "pio": { "peer": "system.iobus.master[1]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 16384, "ret_data32": 4294967295, @@ -181,14 +146,17 @@ }, "cxx_class": "T1000", "fake_jbi": { + "system": "system", "ret_data8": 255, "name": "fake_jbi", + "warn_access": "", "pio": { "peer": "system.iobus.master[11]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 4294967296, "ret_data32": 4294967295, @@ -201,15 +169,19 @@ "type": "IsaFake", "ret_data16": 65535 }, + "intrctrl": "system.intrctrl", "fake_l2esr_2": { + "system": "system", "ret_data8": 255, "name": "fake_l2esr_2", + "warn_access": "", "pio": { "peer": "system.iobus.master[7]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -222,11 +194,13 @@ "type": "IsaFake", "ret_data16": 65535 }, + "system": "system", "eventq_index": 0, "hterm": { "name": "hterm", "output": true, "number": 0, + "intr_control": "system.intrctrl", "eventq_index": 0, "cxx_class": "Terminal", "path": "system.t1000.hterm", @@ -235,14 +209,17 @@ }, "type": "T1000", "fake_l2_4": { + "system": "system", "ret_data8": 255, "name": "fake_l2_4", + "warn_access": "", "pio": { "peer": "system.iobus.master[5]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -256,14 +233,17 @@ "ret_data16": 65535 }, "fake_l2_1": { + "system": "system", "ret_data8": 255, "name": "fake_l2_1", + "warn_access": "", "pio": { "peer": "system.iobus.master[2]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -277,14 +257,17 @@ "ret_data16": 65535 }, "fake_l2_2": { + "system": "system", "ret_data8": 255, "name": "fake_l2_2", + "warn_access": "", "pio": { "peer": "system.iobus.master[3]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -298,14 +281,17 @@ "ret_data16": 65535 }, "fake_l2_3": { + "system": "system", "ret_data8": 255, "name": "fake_l2_3", + "warn_access": "", "pio": { "peer": "system.iobus.master[4]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -322,6 +308,7 @@ "name": "pterm", "output": true, "number": 0, + "intr_control": "system.intrctrl", "eventq_index": 0, "cxx_class": "Terminal", "path": "system.t1000.pterm", @@ -335,7 +322,10 @@ "peer": "system.membus.master[0]", "role": "SLAVE" }, - "pio_latency": 1e-09, + "pio_latency": 2, + "clk_domain": "system.clk_domain", + "system": "system", + "platform": "system.t1000", "eventq_index": 0, "cxx_class": "Iob", "path": "system.t1000.iob", @@ -347,7 +337,11 @@ "peer": "system.iobus.master[13]", "role": "SLAVE" }, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", + "system": "system", + "terminal": "system.t1000.hterm", + "platform": "system.t1000", "eventq_index": 0, "cxx_class": "Uart8250", "path": "system.t1000.hvuart", @@ -356,14 +350,17 @@ }, "name": "t1000", "fake_l2esr_3": { + "system": "system", "ret_data8": 255, "name": "fake_l2esr_3", + "warn_access": "", "pio": { "peer": "system.iobus.master[8]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -377,14 +374,17 @@ "ret_data16": 65535 }, "fake_ssi": { + "system": "system", "ret_data8": 255, "name": "fake_ssi", + "warn_access": "", "pio": { "peer": "system.iobus.master[10]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 268435456, "ret_data32": 4294967295, @@ -398,14 +398,17 @@ "ret_data16": 65535 }, "fake_l2esr_1": { + "system": "system", "ret_data8": 255, "name": "fake_l2esr_1", + "warn_access": "", "pio": { "peer": "system.iobus.master[6]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -419,14 +422,17 @@ "ret_data16": 65535 }, "fake_l2esr_4": { + "system": "system", "ret_data8": 255, "name": "fake_l2esr_4", + "warn_access": "", "pio": { "peer": "system.iobus.master[9]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 8, "ret_data32": 4294967295, @@ -440,14 +446,17 @@ "ret_data16": 65535 }, "fake_clk": { + "system": "system", "ret_data8": 255, "name": "fake_clk", + "warn_access": "", "pio": { "peer": "system.iobus.master[0]", "role": "SLAVE" }, "ret_bad_addr": false, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", "fake_mem": false, "pio_size": 4294967296, "ret_data32": 4294967295, @@ -461,53 +470,36 @@ "ret_data16": 65535 } }, - "partition_desc_addr": 133445976064, - "physmem": [ - { - "latency": 3.0000000000000004e-08, - "name": "physmem0", - "eventq_index": 0, - "latency_var": 0.0, - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "path": "system.physmem0", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[7]", - "role": "SLAVE" - }, - "in_addr_map": true - }, - { - "latency": 3.0000000000000004e-08, - "name": "physmem1", - "eventq_index": 0, - "latency_var": 0.0, - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "path": "system.physmem1", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[8]", - "role": "SLAVE" - }, - "in_addr_map": true - } - ], + "symbolfile": "", + "readfile": "/z/stever/hg/gem5/tests/halt.sh", "hypervisor_addr": 1099243257856, + "mem_ranges": [ + "1048576:68157439", + "2147483648:2415919103" + ], "cxx_class": "SparcSystem", "load_offset": 0, + "reset_bin": "/dist/m5/system/binaries/reset_new.bin", "openboot_addr": 1099243716608, "work_end_ckpt_count": 0, "nvram_addr": 133429198848, + "memories": [ + "system.hypervisor_desc", + "system.physmem1", + "system.partition_desc", + "system.physmem0", + "system.rom", + "system.nvram" + ], "work_begin_ckpt_count": 0, "partition_desc": { - "latency": 3.0000000000000004e-08, + "range": "133445976064:133445984255", + "latency": 60, "name": "partition_desc", "eventq_index": 0, - "latency_var": 0.0, + "clk_domain": "system.clk_domain", + "latency_var": 0, + "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", "path": "system.partition_desc", @@ -521,7 +513,11 @@ }, "clk_domain": { "name": "clk_domain", + "clock": [ + 2 + ], "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", "eventq_index": 0, "cxx_class": "SrcClockDomain", "path": "system.clk_domain", @@ -529,10 +525,13 @@ "domain_id": -1 }, "hypervisor_desc": { - "latency": 3.0000000000000004e-08, + "range": "133446500352:133446508543", + "latency": 60, "name": "hypervisor_desc", "eventq_index": 0, - "latency_var": 0.0, + "clk_domain": "system.clk_domain", + "latency_var": 0, + "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", "path": "system.hypervisor_desc", @@ -544,11 +543,77 @@ }, "in_addr_map": true }, + "membus": { + "default": { + "peer": "system.membus.badaddr_responder.pio", + "role": "MASTER" + }, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "name": "membus", + "badaddr_responder": { + "system": "system", + "ret_data8": 255, + "name": "badaddr_responder", + "warn_access": "", + "pio": { + "peer": "system.membus.default", + "role": "SLAVE" + }, + "ret_bad_addr": true, + "pio_latency": 200, + "clk_domain": "system.clk_domain", + "fake_mem": false, + "pio_size": 8, + "ret_data32": 4294967295, + "eventq_index": 0, + "update_data": false, + "ret_data64": 18446744073709551615, + "cxx_class": "IsaFake", + "path": "system.membus.badaddr_responder", + "pio_addr": 0, + "type": "IsaFake", + "ret_data16": 65535 + }, + "snoop_filter": null, + "clk_domain": "system.clk_domain", + "header_cycles": 1, + "system": "system", + "width": 8, + "eventq_index": 0, + "master": { + "peer": [ + "system.t1000.iob.pio", + "system.t1000.htod.pio", + "system.bridge.slave", + "system.rom.port", + "system.nvram.port", + "system.hypervisor_desc.port", + "system.partition_desc.port", + "system.physmem0.port", + "system.physmem1.port" + ], + "role": "MASTER" + }, + "cxx_class": "CoherentXBar", + "path": "system.membus", + "type": "CoherentXBar", + "use_default_range": false + }, "nvram": { - "latency": 3.0000000000000004e-08, + "range": "133429198848:133429207039", + "latency": 60, "name": "nvram", "eventq_index": 0, - "latency_var": 0.0, + "clk_domain": "system.clk_domain", + "latency_var": 0, + "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", "path": "system.nvram", @@ -561,48 +626,102 @@ "in_addr_map": true }, "eventq_index": 0, + "work_begin_cpu_id_exit": -1, "dvfs_handler": { "enable": false, "name": "dvfs_handler", - "transition_latency": 9.999999999999999e-05, + "sys_clk_domain": "system.clk_domain", + "transition_latency": 200000, "eventq_index": 0, "cxx_class": "DVFSHandler", + "domains": [], "path": "system.dvfs_handler", "type": "DVFSHandler" }, "work_end_exit_count": 0, - "type": "SparcSystem", + "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin", + "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin", "voltage_domain": { + "name": "voltage_domain", "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", "path": "system.voltage_domain", - "type": "VoltageDomain", - "name": "voltage_domain", - "cxx_class": "VoltageDomain" + "type": "VoltageDomain" }, "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": [ + { + "range": "1048576:68157439", + "latency": 60, + "name": "physmem0", + "eventq_index": 0, + "clk_domain": "system.clk_domain", + "latency_var": 0, + "bandwidth": "0.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem0", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[7]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + { + "range": "2147483648:2415919103", + "latency": 60, + "name": "physmem1", + "eventq_index": 0, + "clk_domain": "system.clk_domain", + "latency_var": 0, + "bandwidth": "0.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "path": "system.physmem1", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[8]", + "role": "SLAVE" + }, + "in_addr_map": true + } + ], "work_cpus_ckpt_count": 0, "work_begin_exit_count": 0, - "num_work_ids": 16, "path": "system", + "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin", "cpu_clk_domain": { "name": "cpu_clk_domain", + "clock": [ + 2 + ], "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", "eventq_index": 0, "cxx_class": "SrcClockDomain", "path": "system.cpu_clk_domain", "type": "SrcClockDomain", "domain_id": -1 }, + "nvram_bin": "/dist/m5/system/binaries/nvram1", "mem_mode": "atomic", "name": "system", "init_param": 0, - "system_port": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, + "type": "SparcSystem", + "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin", "load_addr_mask": 1099511627775, "cpu": { - "simpoint_interval": 100000000, "do_statistics_insts": true, "numThreads": 1, "itb": { @@ -613,20 +732,22 @@ "type": "SparcTLB", "size": 64 }, + "simulate_data_stalls": false, "function_trace": false, "do_checkpoint_insts": true, "cxx_class": "AtomicSimpleCPU", "max_loads_all_threads": 0, - "simpoint_profile": false, - "simulate_data_stalls": false, + "system": "system", + "clk_domain": "system.cpu_clk_domain", "function_trace_start": 0, "cpu_id": 0, "width": 1, + "checker": null, "eventq_index": 0, "do_quiesce": true, "type": "AtomicSimpleCPU", "fastmem": false, - "profile": 0.0, + "profile": 0, "icache_port": { "peer": "system.membus.slave[1]", "role": "MASTER" @@ -638,19 +759,16 @@ "name": "interrupts", "cxx_class": "SparcISA::Interrupts" }, + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, "socket_id": 0, "max_insts_all_threads": 0, "path": "system.cpu", - "isa": [ - { - "eventq_index": 0, - "path": "system.cpu.isa", - "type": "SparcISA", - "name": "isa", - "cxx_class": "SparcISA::ISA" - } - ], + "max_loads_any_thread": 0, "switched_out": false, + "workload": [], "name": "cpu", "dtb": { "name": "dtb", @@ -660,14 +778,20 @@ "type": "SparcTLB", "size": 64 }, + "simpoint_start_insts": [], "max_insts_any_thread": 0, "simulate_inst_stalls": false, - "progress_interval": 0.0, - "dcache_port": { - "peer": "system.membus.slave[2]", - "role": "MASTER" - }, - "max_loads_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "SparcISA", + "name": "isa", + "cxx_class": "SparcISA::ISA" + } + ], "tracer": { "eventq_index": 0, "path": "system.cpu.tracer", @@ -677,11 +801,12 @@ } }, "intrctrl": { + "name": "intrctrl", + "sys": "system", "eventq_index": 0, + "cxx_class": "IntrControl", "path": "system.intrctrl", - "type": "IntrControl", - "name": "intrctrl", - "cxx_class": "IntrControl" + "type": "IntrControl" }, "disk0": { "name": "disk0", @@ -692,35 +817,40 @@ "image": { "read_only": false, "name": "image", + "cxx_class": "CowDiskImage", + "eventq_index": 0, "child": { "read_only": true, "name": "child", "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.disk0.image.child", + "image_file": "/dist/m5/system/disks/disk.s10hw2", "type": "RawDiskImage" }, - "eventq_index": 0, - "cxx_class": "CowDiskImage", "path": "system.disk0.image", - "table_size": 65536, - "type": "CowDiskImage" + "image_file": "", + "type": "CowDiskImage", + "table_size": 65536 }, - "pio_latency": 1.0000000000000001e-07, + "pio_latency": 200, + "clk_domain": "system.clk_domain", + "system": "system", "eventq_index": 0, "cxx_class": "MmDisk", "path": "system.disk0", "pio_addr": 134217728000, "type": "MmDisk" }, - "hypervisor_desc_addr": 133446500352, "reset_addr": 1099243192320, + "hypervisor_desc_addr": 133446500352, + "partition_desc_addr": 133445976064, "work_item_id": -1, - "work_begin_cpu_id_exit": -1 + "num_work_ids": 16 }, - "time_sync_period": 0.1, + "time_sync_period": 200000000, "eventq_index": 0, - "time_sync_spin_threshold": 9.999999999999999e-05, + "time_sync_spin_threshold": 200000, "cxx_class": "Root", "path": "root", "time_sync_enable": false, diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr index c7cb2a7c3..2807da6d7 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -22,6 +22,18 @@ warn: rounding error > tolerance 0.145519 rounded to 0 warn: rounding error > tolerance 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 001061453..0f037ca30 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 12 2014 11:27:38 -gem5 started May 12 2014 11:28:05 +gem5 compiled Sep 21 2014 21:13:41 +gem5 started Sep 21 2014 21:13:51 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /z/stever/hg/gem5/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 3676ead42..bd8f18574 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.233778 # Nu sim_ticks 4467555024 # Number of ticks simulated final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 2578014 # Simulator instruction rate (inst/s) -host_op_rate 2579027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5168737 # Simulator tick rate (ticks/s) -host_mem_usage 527944 # Number of bytes of host memory used -host_seconds 864.34 # Real time elapsed on the host +host_inst_rate 2544690 # Simulator instruction rate (inst/s) +host_op_rate 2545690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5101926 # Simulator tick rate (ticks/s) +host_mem_usage 520472 # Number of bytes of host memory used +host_seconds 875.66 # Real time elapsed on the host sim_insts 2228284650 # Number of instructions simulated sim_ops 2229160714 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,60 +21,6 @@ system.hypervisor_desc.bw_read::cpu.data 7517 # To system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s) system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s) system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory -system.nvram.bytes_read::total 284 # Number of bytes read from this memory -system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory -system.nvram.bytes_written::total 92 # Number of bytes written to this memory -system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory -system.nvram.num_reads::total 284 # Number of read requests responded to by this memory -system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory -system.nvram.num_writes::total 92 # Number of write requests responded to by this memory -system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory -system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory -system.rom.bytes_read::total 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory -system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory -system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory -system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory -system.rom.num_reads::total 195123 # Number of read requests responded to by this memory -system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) -system.physmem0.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory -system.physmem0.bytes_read::cpu.data 97534024 # Number of bytes read from this memory -system.physmem0.bytes_read::total 709825348 # Number of bytes read from this memory -system.physmem0.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory -system.physmem0.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory -system.physmem0.bytes_written::cpu.data 15400223 # Number of bytes written to this memory -system.physmem0.bytes_written::total 15400223 # Number of bytes written to this memory -system.physmem0.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory -system.physmem0.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory -system.physmem0.num_reads::total 165224885 # Number of read requests responded to by this memory -system.physmem0.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory -system.physmem0.num_writes::total 1927067 # Number of write requests responded to by this memory -system.physmem0.num_other::cpu.data 14 # Number of other requests responded to by this memory -system.physmem0.num_other::total 14 # Number of other requests responded to by this memory -system.physmem0.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s) -system.physmem0.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s) -system.physmem0.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s) -system.physmem0.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem0.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem0.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s) -system.physmem0.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s) -system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s) -system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s) -system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s) system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory @@ -107,11 +53,139 @@ system.partition_desc.bw_read::cpu.data 2169 # To system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s) system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s) system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 5163367605 # Throughput (bytes/s) -system.membus.data_through_bus 11533814443 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 15555081 # Throughput (bytes/s) -system.iobus.data_through_bus 34746591 # Total data (bytes) +system.physmem0.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory +system.physmem0.bytes_read::cpu.data 97534024 # Number of bytes read from this memory +system.physmem0.bytes_read::total 709825348 # Number of bytes read from this memory +system.physmem0.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory +system.physmem0.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory +system.physmem0.bytes_written::cpu.data 15400223 # Number of bytes written to this memory +system.physmem0.bytes_written::total 15400223 # Number of bytes written to this memory +system.physmem0.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory +system.physmem0.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory +system.physmem0.num_reads::total 165224885 # Number of read requests responded to by this memory +system.physmem0.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory +system.physmem0.num_writes::total 1927067 # Number of write requests responded to by this memory +system.physmem0.num_other::cpu.data 14 # Number of other requests responded to by this memory +system.physmem0.num_other::total 14 # Number of other requests responded to by this memory +system.physmem0.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s) +system.physmem0.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s) +system.physmem0.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s) +system.physmem0.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem0.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem0.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem0.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s) +system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s) +system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s) +system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory +system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory +system.rom.bytes_read::total 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory +system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory +system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory +system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory +system.rom.num_reads::total 195123 # Number of read requests responded to by this memory +system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory +system.nvram.bytes_read::total 284 # Number of bytes read from this memory +system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory +system.nvram.bytes_written::total 92 # Number of bytes written to this memory +system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory +system.nvram.num_reads::total 284 # Number of read requests responded to by this memory +system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory +system.nvram.num_writes::total 92 # Number of write requests responded to by this memory +system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 2573267624 # Transaction distribution +system.membus.trans_dist::ReadResp 2573267624 # Transaction distribution +system.membus.trans_dist::WriteReq 189322556 # Transaction distribution +system.membus.trans_dist::WriteResp 189322556 # Transaction distribution +system.membus.trans_dist::SwapReq 5403081 # Transaction distribution +system.membus.trans_dist::SwapResp 5403081 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 306145662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4159053420 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 4465415230 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8712246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 28158270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1033506566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1070571292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5535986522 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 612291324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8318106840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8930830460 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34746591 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 112934471 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2454584131 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 2602983983 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11533814443 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2767993261 # Request fanout histogram +system.membus.snoop_fanout::mean 0.806616 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.394951 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 535285646 19.34% 19.34% # Request fanout histogram +system.membus.snoop_fanout::1 2232707615 80.66% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2767993261 # Request fanout histogram +system.iobus.trans_dist::ReadReq 4348554 # Transaction distribution +system.iobus.trans_dist::ReadResp 4348554 # Transaction distribution +system.iobus.trans_dist::WriteReq 7569 # Transaction distribution +system.iobus.trans_dist::WriteResp 7569 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_membnks.pio 40 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_1.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_2.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_3.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_4.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.fake_jbi.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.t1000.hvuart.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682882 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 8712246 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_membnks.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_1.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_2.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_3.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_4.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_1.pio 16 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_2.pio 16 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_3.pio 16 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_4.pio 16 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.fake_jbi.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14609 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34731524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 34746591 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 2 # Clock period in ticks system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started