From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 18 Mar 2013 14:05:15 +0000 (+0100)
Subject: More TODOs in README
X-Git-Tag: yosys-0.2.0~712
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71de6660036c7cea95884554382bc2913af36252;p=yosys.git

More TODOs in README
---

diff --git a/README b/README
index 89aa0544a..cbd77bb17 100644
--- a/README
+++ b/README
@@ -197,9 +197,15 @@ TODOs / Open Bugs
 
 - Write "design and implementation of.." document
 
+  - Source tree layout
+  - Data formats (c++ classes, etc.)
+  - Interne misc. frameworks (log, select)
+  - Build system and pass registration
+  - Internal cell library
+
 - Add brief source code documentation to:
 
-   - Most passes and kernel functionalities
+  - Most passes and kernel functionalities
 
 - Implement missing Verilog 2005 features: