From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Jul 2020 19:37:14 +0000 (+0100)
Subject: ALU output stage, change logic slightly
X-Git-Tag: div_pipeline~126
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71e09d8ed7d520728ec93c34e13f0ba29252860c;p=soc.git

ALU output stage, change logic slightly
test for oe/ok then set xer/ov data/ok if true
---

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 98e653a5..3ea71b56 100644
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -28,9 +28,10 @@ class ALUOutputStage(CommonOutputStage):
         # copy overflow and sticky-overflow.  indicate to CompALU if they
         # are actually required (oe enabled/set) otherwise the CompALU
         # can (will) ignore them.
-        comb += self.o.xer_so.data.eq(self.so)
-        comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok)
-        comb += self.o.xer_ov.data.eq(xer_ov_i)
-        comb += self.o.xer_ov.ok.eq(op.oe.oe & op.oe.oe_ok) # OV/32 is to be set
+        with m.If(op.oe.oe & op.oe.oe_ok):
+            comb += self.o.xer_so.data.eq(self.so)
+            comb += self.o.xer_so.ok.eq(1)
+            comb += self.o.xer_ov.data.eq(xer_ov_i)
+            comb += self.o.xer_ov.ok.eq(1) # OV/32 is to be set
 
         return m