From: lkcl <lkcl@web>
Date: Fri, 14 Apr 2023 23:43:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls008_v1~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71e4b88ad53acbf21be756d9161a271a6b96d7eb;p=libreriscv.git

---

diff --git a/openpower/sv/svp64-single.mdwn b/openpower/sv/svp64-single.mdwn
index 97a352415..0e07dbcc0 100644
--- a/openpower/sv/svp64-single.mdwn
+++ b/openpower/sv/svp64-single.mdwn
@@ -6,9 +6,11 @@ encodings concepts:
 
 * 24 bits available
 * vectors not applicable thus EXTRA4 may bring 4 bits (CR Fields) quantity 3of
-  for a total of 12 bits.
-* elwidth src/dest is 2x4 for a total 4 bits
-* single predicate mask (one bit) is 1 for type, 3 for source, totals another 4 bits
+  for a total of 12 bits. GPR/FPR/VR 3 bits extends VR to 512 regs (!) and
+  GPR/FPR to 256 (!)
+* elwidth src/dest is 2x2 for a total 4 bits
+* single predicate mask (one bit) is 1 for type
+  (GPR/VR and CRfield), 3 for source, totals another 4 bits
 
 totals 20 bits leaving 4 for a "Mode".
 
@@ -18,5 +20,5 @@ totals 20 bits leaving 4 for a "Mode".
 
 potentially this leaves 2 bits for SUBVL.  an advantage of that is
 that VSX could be over-ridden to have the number of PackedSIMD
-element operations redefined
+element operations redefined?