From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 3 May 2019 13:29:44 +0000 (+0200)
Subject: Merge pull request #976 from YosysHQ/clifford/fix974
X-Git-Tag: yosys-0.9~157
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71ede7cb05ae35c90eccb80ffc413b4559ba7e60;p=yosys.git

Merge pull request #976 from YosysHQ/clifford/fix974

Fix width detection of memory access with bit slice
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71ede7cb05ae35c90eccb80ffc413b4559ba7e60