From: lkcl <lkcl@web>
Date: Tue, 4 Oct 2022 12:11:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~189
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71f2389b8d2acd164b484b34ede7037a6a882655;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index 6b367e1be..db96851bc 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -227,7 +227,8 @@ Summary so far:
 * failfirst needs to be an illegal exception if all-scalar
 * non-zeroing predication on all-scalar with VL>1 requires
   all relevant bits to be set, this changes to the **first**
-  bit for auto-VL=1
+  bit for auto-VL=1.  requires an extra reduction instruction.
+* sv.branches should not be touched. at all.
 
 ## answers to 2, RM Modes