From: Wladimir J. van der Laan Date: Sun, 3 Apr 2016 12:26:56 +0000 (+0200) Subject: Fix a few typos in the manual X-Git-Tag: yosys-0.7~269^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71f9f40fa9e44351f7a9ebabff622c2569689745;p=yosys.git Fix a few typos in the manual --- diff --git a/manual/manual.tex b/manual/manual.tex index ecc7e4c99..67982cbc8 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -151,14 +151,14 @@ availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful. In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was -developped. This document covers the design and implementation of this tool. +developed. This document covers the design and implementation of this tool. At the moment the main focus of Yosys lies on the high-level aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used by Yosys to perform advanced gate-level optimizations. An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced -by Yosys in this tests where successflly verified using formal verification +by Yosys in this tests where successfully verified using formal verification and are comparable in quality to the results produced by a commercial synthesis tool. @@ -172,7 +172,7 @@ University of Technology \cite{BACC}. AIG & And-Inverter-Graph \\ ASIC & Application-Specific Integrated Circuit \\ AST & Abstract Syntax Tree \\ -BDD & Binary Decicion Diagram \\ +BDD & Binary Decision Diagram \\ BLIF & Berkeley Logic Interchange Format \\ EDA & Electronic Design Automation \\ EDIF & Electronic Design Interchange Format \\