From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 30 Oct 2018 09:14:48 +0000 (+0100)
Subject: boards/targets/ulx3s: reduce l2_size
X-Git-Tag: 24jan2021_ls180~1531
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71fc34d7b62e864e9c9d7e2b7a74865e704b5ca9;p=litex.git

boards/targets/ulx3s: reduce l2_size
---

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 0574aa79..1e1a3006 100755
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -52,6 +52,7 @@ class BaseSoC(SoCSDRAM):
         platform = ulx3s.Platform(toolchain="prjtrellis")
         sys_clk_freq = int(25e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+                          l2_size=32,
                           integrated_rom_size=0x8000,
                           **kwargs)