From: Jacob Lifshay Date: Fri, 26 May 2023 05:09:31 +0000 (-0700) Subject: fcvttg CR0 fields (except SO) are undefined when RT is not written X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72076851a4927c15c077db046d2ec0a234033fa0;p=libreriscv.git fcvttg CR0 fields (except SO) are undefined when RT is not written this can occur even when fp traps are disabled in MSR, so writing "on exceptions" is incorrect. --- diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index a9c7efaa5..ca1749c2f 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -590,7 +590,8 @@ if the numerical value of the FP number is not 100% accurately preserved (due to truncation or saturation and including when the FP number was NaN) then this is considered to be an Integer Overflow condition, and CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions -that overflow. +that overflow. When `RT` is not written (`vex_flag = 1`), all CR0 bits +except SO are undefined. Special Registers altered: @@ -758,7 +759,8 @@ if the numerical value of the FP number is not 100% accurately preserved (due to truncation or saturation and including when the FP number was NaN) then this is considered to be an Integer Overflow condition, and CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions -that overflow. +that overflow. When `RT` is not written (`vex_flag = 1`), all CR0 bits +except SO are undefined. Special Registers altered: