From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 31 Mar 2022 13:44:24 +0000 (+0100)
Subject: invert cs_n pin in Tercel
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72113acbd8ad50f8cbbf6f75aeb6da29d9abaabe;p=soc.git

invert cs_n pin in Tercel
---

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index 328bf661..3e71a3bf 100644
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -168,12 +168,11 @@ class Tercel(Elaboratable):
         if pins is not None:
             comb += pins.dq.o.eq(self.dq_out)
             comb += pins.dq.oe.eq(self.dq_direction)
-            comb += pins.dq.oe.eq(self.dq_direction)
             comb += pins.dq.o_clk.eq(ClockSignal())
             comb += self.dq_in.eq(pins.dq.i)
             comb += pins.dq.i_clk.eq(ClockSignal())
             # XXX invert handled by SPIFlashResource
-            comb += pins.cs.eq(~self.cs_n_out)
+            comb += pins.cs_n.eq(self.cs_n_out)
             # ECP5 needs special handling for the SPI clock, sigh.
             if self.lattice_ecp5_usrmclk:
                 m.submodules += Instance("USRMCLK",