From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 25 Feb 2019 23:34:02 +0000 (-0800)
Subject: read_aiger to accept empty string for clk_name, passable only if no latches
X-Git-Tag: working-ls180~1237^2~260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=721f6a14fb632b671ba10ed13cafad1263e2b073;p=yosys.git

read_aiger to accept empty string for clk_name, passable only if no latches
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index c8ba1bffd..a64729a27 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -524,6 +524,7 @@ void AigerReader::parse_aiger_ascii()
     // Parse latches
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
+        log_assert(clk_name != "");
         clk_wire = module->wire(clk_name);
         log_assert(!clk_wire);
         log_debug("Creating %s\n", clk_name.c_str());
@@ -654,6 +655,7 @@ void AigerReader::parse_aiger_binary()
     // Parse latches
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
+        log_assert(clk_name != "");
         clk_wire = module->wire(clk_name);
         log_assert(!clk_wire);
         log_debug("Creating %s\n", clk_name.c_str());
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 90234ea33..68e54f518 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -523,8 +523,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		bool builtin_lib = liberty_file.empty();
 		RTLIL::Design *mapped_design = new RTLIL::Design;
 		//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
-		buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
-		AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
+		AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */);
 		reader.parse_xaiger();
 
 		ifs.close();