From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 19:08:59 +0000 (-0700)
Subject: abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
X-Git-Tag: working-ls180~549^2~28
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=722540dbf942d2b8acbaf7372001c7d982eb2845;p=yosys.git

abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ddda1bd5a..abb9ae30f 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -644,6 +644,7 @@ struct XAigerWriter
 
 				SigBit Q = sigmap(cell->getPort(ID::Q));
 				State init = init_map.at(Q, State::Sx);
+				log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init));
 				if (init == State::S1)
 					write_s_buffer(1);
 				else if (init == State::S0)
diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v
index b04a5b64f..5f1822485 100644
--- a/techlibs/common/abc9_map.v
+++ b/techlibs/common/abc9_map.v
@@ -2,20 +2,24 @@
 module $_DFF_x_(input C, D, output Q);
   parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
   parameter _TECHMAP_CELLTYPE_ = "";
-  generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
-    wire _TECHMAP_FAIL_ = 1;
-  else if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
-    wire D_;
-    $__DFF_N__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
-    $_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
+  wire D_;
+  generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
+    if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
+      $__DFF_N__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
+      $_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
+    end
+    else
+      $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));// hide from abc9 using $__ prefix
   end
   else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
-    wire D_;
-    $__DFF_P__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
-    $_DFF_P_ ff (.C(C), .D(D_), .Q(Q));
+    if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
+      $__DFF_P__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
+      $_DFF_P_ ff (.C(C), .D(D_), .Q(Q));
+    end
+    else
+      $__DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix
   end
   else if (_TECHMAP_CELLTYPE_ != "")
     $error("Unrecognised _TECHMAP_CELLTYPE_");
   endgenerate
-  wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v
index 0fd07207d..4dfac0cbb 100644
--- a/techlibs/common/abc9_unmap.v
+++ b/techlibs/common/abc9_unmap.v
@@ -10,3 +10,15 @@ module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1);
     $error("Unrecognised _TECHMAP_CELLTYPE_");
   endgenerate
 endmodule
+
+(* techmap_celltype = "$__DFF_N_ $__DFF_P_" *)
+module $__DFF_N__$abc9_flop(input C, D, output Q);
+  parameter _TECHMAP_CELLTYPE_ = "";
+  generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_")
+    $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
+  else if (_TECHMAP_CELLTYPE_ == "$__DFF_P_")
+    $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
+  else if (_TECHMAP_CELLTYPE_ != "")
+    $error("Unrecognised _TECHMAP_CELLTYPE_");
+  endgenerate
+endmodule
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 7a3a503e4..9586091c4 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -50,7 +50,7 @@ $_DFF_P_ ff(.C(clk), .D(d), .Q(w));
 assign q = w;
 endmodule
 EOT
-equiv_opt abc9 -lut 4 -dff
+equiv_opt -assert abc9 -lut 4 -dff
 design -load postopt
 cd abc9_test036
 select -assert-count 1 t:$_DFF_P_
@@ -69,8 +69,27 @@ specify
 endspecify
 endmodule
 
-module top(input [1:0] i, output o);
+module abc9_test037(input [1:0] i, output o);
 LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
 endmodule
 EOT
 abc9
+
+
+design -reset
+read_verilog -icells <<EOT
+module abc9_test038(input clk, output w, x, y);
+(* init=1'b1 *) wire w;
+$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
+(* init=1'bx *) wire x;
+$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
+(* init=1'b0 *) wire y;
+$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
+endmodule
+EOT
+simplemap
+equiv_opt abc9 -lut 4 -dff
+design -load postopt
+cd abc9_test038
+select -assert-count 2 t:$_DFF_N_
+select -assert-none c:ff1 c:ff2 %% c:* %D