From: Gabe Black Date: Mon, 27 Aug 2007 04:45:40 +0000 (-0700) Subject: Merge with head X-Git-Tag: m5_2.0_beta4~163 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7227ab5f223eb5f4d3ce80ea16bff5f87c3300b6;p=gem5.git Merge with head --HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6 --- diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 043c65a4a..7d344fa33 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -364,6 +364,8 @@ DefaultFetch::processCacheCompletion(PacketPtr pkt) DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); + assert(!pkt->wasNacked()); + // Only change the status if it's still waiting on the icache access // to return. if (fetchStatus[tid] != IcacheWaitResponse || diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index c71a0ad9d..8ed6f7f54 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -80,6 +80,8 @@ template bool LSQ::DcachePort::recvTiming(PacketPtr pkt) { + if (pkt->isError()) + DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr()); if (pkt->isResponse()) { lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt); } diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 4ab149cee..71b416c9c 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -83,6 +83,8 @@ LSQUnit::completeDataAccess(PacketPtr pkt) //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); + assert(!pkt->wasNacked()); + if (isSwitchedOut() || inst->isSquashed()) { iewStage->decrWb(inst->seqNum); } else { diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 234803be5..06f52e30e 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -328,6 +328,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) dcache_latency += dcachePort.sendAtomic(&pkt); } dcache_access = true; + assert(!pkt.isError()); if (req->isLocked()) { @@ -611,6 +612,7 @@ AtomicSimpleCPU::tick() else icache_latency = icachePort.sendAtomic(&ifetch_pkt); + assert(!ifetch_pkt.isError()); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 1e1f43f7d..8d1cf9a17 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -583,7 +583,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process() bool TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) { - if (pkt->isResponse()) { + if (pkt->isResponse() && !pkt->wasNacked()) { // delay processing of returned data until next CPU clock edge Tick next_tick = cpu->nextCycle(curTick); @@ -686,7 +686,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port) bool TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) { - if (pkt->isResponse()) { + if (pkt->isResponse() && !pkt->wasNacked()) { // delay processing of returned data until next CPU clock edge Tick next_tick = cpu->nextCycle(curTick); diff --git a/src/dev/alpha/console.cc b/src/dev/alpha/console.cc index 84425945b..493a21f99 100644 --- a/src/dev/alpha/console.cc +++ b/src/dev/alpha/console.cc @@ -107,6 +107,7 @@ AlphaConsole::read(PacketPtr pkt) Addr daddr = pkt->getAddr() - pioAddr; pkt->allocate(); + pkt->makeAtomicResponse(); switch (pkt->getSize()) { @@ -188,7 +189,6 @@ AlphaConsole::read(PacketPtr pkt) default: pkt->setBadAddress(); } - pkt->makeAtomicResponse(); return pioDelay; } diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 797f82c13..81a111f71 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -57,7 +57,7 @@ using namespace Net; IGbE::IGbE(const Params *p) : EtherDevice(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control), rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false), - txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this), + txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this), tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this), rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size), txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock) @@ -113,7 +113,7 @@ EtherInt* IGbE::getEthPort(const std::string &if_name, int idx) { - if (if_name == "interface" && !etherInt) { + if (if_name == "interface") { if (etherInt->getPeer()) panic("Port already connected to\n"); return etherInt; @@ -504,8 +504,13 @@ IGbE::write(PacketPtr pkt) break; case REG_RDT: regs.rdt = val; - rxTick = true; - restartClock(); + DPRINTF(EthernetSM, "RXS: RDT Updated.\n"); + if (getState() == SimObject::Running) { + DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n"); + rxDescCache.fetchDescriptors(); + } else { + DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n"); + } break; case REG_RDTR: regs.rdtr = val; @@ -531,8 +536,13 @@ IGbE::write(PacketPtr pkt) break; case REG_TDT: regs.tdt = val; - txTick = true; - restartClock(); + DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n"); + if (getState() == SimObject::Running) { + DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n"); + txDescCache.fetchDescriptors(); + } else { + DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n"); + } break; case REG_TIDV: regs.tidv = val; @@ -566,33 +576,47 @@ IGbE::postInterrupt(IntTypes t, bool now) assert(t); // Interrupt is already pending - if (t & regs.icr()) + if (t & regs.icr() && !now) return; - if (regs.icr() & regs.imr) - { - regs.icr = regs.icr() | t; - if (!interEvent.scheduled()) - interEvent.schedule(curTick + Clock::Int::ns * 256 * - regs.itr.interval()); - } else { - regs.icr = regs.icr() | t; - if (regs.itr.interval() == 0 || now) { - if (interEvent.scheduled()) - interEvent.deschedule(); - cpuPostInt(); - } else { - DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n", - Clock::Int::ns * 256 * regs.itr.interval()); - if (!interEvent.scheduled()) - interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval()); + regs.icr = regs.icr() | t; + if (regs.itr.interval() == 0 || now) { + if (interEvent.scheduled()) { + interEvent.deschedule(); } + cpuPostInt(); + } else { + DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n", + Clock::Int::ns * 256 * regs.itr.interval()); + if (!interEvent.scheduled()) { + interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval()); + } } } +void +IGbE::delayIntEvent() +{ + cpuPostInt(); +} + + void IGbE::cpuPostInt() { + + if (!(regs.icr() & regs.imr)) { + DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n"); + return; + } + + DPRINTF(Ethernet, "Posting Interrupt\n"); + + + if (interEvent.scheduled()) { + interEvent.deschedule(); + } + if (rdtrEvent.scheduled()) { regs.icr.rxt0(1); rdtrEvent.deschedule(); @@ -613,7 +637,9 @@ IGbE::cpuPostInt() regs.icr.int_assert(1); DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n", regs.icr()); + intrPost(); + } void @@ -630,20 +656,28 @@ IGbE::cpuClearInt() void IGbE::chkInterrupt() { + DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(), + regs.imr); // Check if we need to clear the cpu interrupt if (!(regs.icr() & regs.imr)) { + DPRINTF(Ethernet, "Mask cleaned all interrupts\n"); if (interEvent.scheduled()) interEvent.deschedule(); if (regs.icr.int_assert()) cpuClearInt(); } + DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", regs.itr(), regs.itr.interval()); if (regs.icr() & regs.imr) { if (regs.itr.interval() == 0) { cpuPostInt(); } else { - if (!interEvent.scheduled()) + DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n"); + if (!interEvent.scheduled()) { + DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns + * 256 * regs.itr.interval()); interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval()); + } } } @@ -682,6 +716,7 @@ IGbE::RxDescCache::pktComplete() RxDesc *desc; desc = unusedCache.front(); + uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ; desc->len = htole((uint16_t)(pktPtr->length + crcfixup)); DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n", @@ -754,9 +789,10 @@ IGbE::RxDescCache::pktComplete() if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) { DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", igbe->regs.radv.idv() * igbe->intClock()); - if (!igbe->radvEvent.scheduled()) + if (!igbe->radvEvent.scheduled()) { igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() * igbe->intClock()); + } } // if neither radv or rdtr, maybe itr is set... @@ -775,10 +811,13 @@ IGbE::RxDescCache::pktComplete() DPRINTF(EthernetDesc, "Processing of this descriptor complete\n"); unusedCache.pop_front(); usedCache.push_back(desc); + + pktPtr = NULL; enableSm(); pktDone = true; igbe->checkDrain(); + } void @@ -843,11 +882,13 @@ IGbE::TxDescCache::getPacketSize() // I think we can just ignore these for now? desc = unusedCache.front(); + DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", desc->d1, + desc->d2); // is this going to be a tcp or udp packet? isTcp = TxdOp::tcp(desc) ? true : false; // make sure it's ipv4 - assert(TxdOp::ip(desc)); + //assert(TxdOp::ip(desc)); TxdOp::setDd(desc); unusedCache.pop_front(); @@ -894,7 +935,6 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "DMA of packet complete\n"); - desc = unusedCache.front(); assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc)); @@ -951,20 +991,21 @@ IGbE::TxDescCache::pktComplete() ip->sum(cksum(ip)); DPRINTF(EthernetDesc, "Calculated IP checksum\n"); } - if (TxdOp::txsm(desc)) { - if (isTcp) { - TcpPtr tcp(ip); - assert(tcp); - tcp->sum(0); - tcp->sum(cksum(tcp)); - DPRINTF(EthernetDesc, "Calculated TCP checksum\n"); - } else { - UdpPtr udp(ip); - assert(udp); - udp->sum(0); - udp->sum(cksum(udp)); - DPRINTF(EthernetDesc, "Calculated UDP checksum\n"); - } + if (TxdOp::txsm(desc)) { + TcpPtr tcp(ip); + UdpPtr udp(ip); + if (tcp) { + tcp->sum(0); + tcp->sum(cksum(tcp)); + DPRINTF(EthernetDesc, "Calculated TCP checksum\n"); + } else if (udp) { + assert(udp); + udp->sum(0); + udp->sum(cksum(udp)); + DPRINTF(EthernetDesc, "Calculated UDP checksum\n"); + } else { + panic("Told to checksum, but don't know how\n"); + } } } @@ -979,9 +1020,10 @@ IGbE::TxDescCache::pktComplete() if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) { DPRINTF(EthernetDesc, "setting tadv\n"); - if (!igbe->tadvEvent.scheduled()) + if (!igbe->tadvEvent.scheduled()) { igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() * igbe->intClock()); + } } } @@ -1103,8 +1145,11 @@ IGbE::checkDrain() if (!drainEvent) return; - if (rxDescCache.hasOutstandingEvents() || - txDescCache.hasOutstandingEvents()) { + txFifoTick = false; + txTick = false; + rxTick = false; + if (!rxDescCache.hasOutstandingEvents() && + !txDescCache.hasOutstandingEvents()) { drainEvent->process(); drainEvent = NULL; } @@ -1124,6 +1169,7 @@ IGbE::txStateMachine() // iteration we'll get the rest of the data if (txPacket && txDescCache.packetAvailable() && txPacket->length) { bool success; + DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n"); success = txFifo.push(txPacket); txFifoTick = true; @@ -1146,11 +1192,12 @@ IGbE::txStateMachine() if (!txDescCache.packetWaiting()) { if (txDescCache.descLeft() == 0) { + postInterrupt(IT_TXQE); + txDescCache.writeback(0); DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing " "writeback stopping ticking and posting TXQE\n"); - txDescCache.writeback(0); + txDescCache.fetchDescriptors(); txTick = false; - postInterrupt(IT_TXQE, true); return; } @@ -1170,12 +1217,13 @@ IGbE::txStateMachine() txFifo.reserve(size); txDescCache.getPacketData(txPacket); } else if (size <= 0) { + DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size); DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n"); txDescCache.writeback(0); } else { + txDescCache.writeback((cacheBlockSize()-1)>>4); DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space " "available in FIFO\n"); - txDescCache.writeback((cacheBlockSize()-1)>>4); txTick = false; } @@ -1190,6 +1238,7 @@ bool IGbE::ethRxPkt(EthPacketPtr pkt) { DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n"); + if (!regs.rctl.en()) { DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n"); return true; @@ -1235,8 +1284,6 @@ IGbE::rxStateMachine() } if (descLeft == 0) { - DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing" - " writeback and stopping ticking\n"); rxDescCache.writeback(0); rxTick = false; } @@ -1310,16 +1357,26 @@ IGbE::txWire() return; } + if (etherInt->askBusy()) { + // We'll get woken up when the packet ethTxDone() gets called + txFifoTick = false; + } else { + if (DTRACE(EthernetSM)) { + IpPtr ip(txFifo.front()); + if (ip) + DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n", + ip->id()); + else + DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n"); + } - if (etherInt->sendPacket(txFifo.front())) { + bool r = etherInt->sendPacket(txFifo.front()); + assert(r); + r += 1; DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n", txFifo.avail()); txFifo.pop(); - } else { - // We'll get woken up when the packet ethTxDone() gets called - txFifoTick = false; } - } void @@ -1348,7 +1405,8 @@ IGbE::ethTxDone() // fifo to send another packet // tx sm to put more data into the fifo txFifoTick = true; - txTick = true; + if (txDescCache.descLeft() != 0) + txTick = true; restartClock(); DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n"); @@ -1387,15 +1445,15 @@ IGbE::serialize(std::ostream &os) SERIALIZE_SCALAR(radv_time); if (tidvEvent.scheduled()) - rdtr_time = tidvEvent.when(); + tidv_time = tidvEvent.when(); SERIALIZE_SCALAR(tidv_time); if (tadvEvent.scheduled()) - rdtr_time = tadvEvent.when(); + tadv_time = tadvEvent.when(); SERIALIZE_SCALAR(tadv_time); if (interEvent.scheduled()) - rdtr_time = interEvent.when(); + inter_time = interEvent.when(); SERIALIZE_SCALAR(inter_time); nameOut(os, csprintf("%s.TxDescCache", name())); diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index 95eac4f82..50101325a 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -147,9 +147,10 @@ class IGbE : public EtherDevice /** Send an interrupt to the cpu */ + void delayIntEvent(); void cpuPostInt(); // Event to moderate interrupts - EventWrapper interEvent; + EventWrapper interEvent; /** Clear the interupt line to the cpu */ @@ -177,6 +178,7 @@ class IGbE : public EtherDevice virtual void updateHead(long h) = 0; virtual void enableSm() = 0; virtual void intAfterWb() const {} + virtual void fetchAfterWb() = 0; std::deque usedCache; std::deque unusedCache; @@ -283,12 +285,6 @@ class IGbE : public EtherDevice for (int x = 0; x < wbOut; x++) memcpy(&wbBuf[x], usedCache[x], sizeof(T)); - for (int x = 0; x < wbOut; x++) { - assert(usedCache.size()); - delete usedCache[0]; - usedCache.pop_front(); - }; - assert(wbOut); igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)), @@ -307,7 +303,6 @@ class IGbE : public EtherDevice else max_to_fetch = descLen() - cachePnt; - max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() - unusedCache.size())); @@ -369,10 +364,16 @@ class IGbE : public EtherDevice */ void wbComplete() { + long curHead = descHead(); #ifndef NDEBUG long oldHead = curHead; #endif + for (int x = 0; x < wbOut; x++) { + assert(usedCache.size()); + delete usedCache[0]; + usedCache.pop_front(); + }; curHead += wbOut; wbOut = 0; @@ -387,12 +388,17 @@ class IGbE : public EtherDevice oldHead, curHead); // If we still have more to wb, call wb now + bool oldMoreToWb = moreToWb; if (moreToWb) { DPRINTF(EthernetDesc, "Writeback has more todo\n"); writeback(wbAlignment); } + intAfterWb(); - igbe->checkDrain(); + if (!oldMoreToWb) { + igbe->checkDrain(); + } + fetchAfterWb(); } @@ -502,6 +508,10 @@ class IGbE : public EtherDevice virtual long descTail() const { return igbe->regs.rdt(); } virtual void updateHead(long h) { igbe->regs.rdh(h); } virtual void enableSm(); + virtual void fetchAfterWb() { + if (!igbe->rxTick && igbe->getState() == SimObject::Running) + fetchDescriptors(); + } bool pktDone; @@ -544,7 +554,13 @@ class IGbE : public EtherDevice virtual long descLen() const { return igbe->regs.tdlen() >> 4; } virtual void updateHead(long h) { igbe->regs.tdh(h); } virtual void enableSm(); - virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW);} + virtual void intAfterWb() const { + igbe->postInterrupt(iGbReg::IT_TXDW); + } + virtual void fetchAfterWb() { + if (!igbe->txTick && igbe->getState() == SimObject::Running) + fetchDescriptors(); + } bool pktDone; bool isTcp; diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc index 9d62aecba..9525436c0 100644 --- a/src/dev/isa_fake.cc +++ b/src/dev/isa_fake.cc @@ -56,6 +56,7 @@ Tick IsaFake::read(PacketPtr pkt) { + pkt->makeAtomicResponse(); if (params()->warn_access != "") warn("Device %s accessed by read to address %#x size=%d\n", name(), pkt->getAddr(), pkt->getSize()); @@ -83,7 +84,6 @@ IsaFake::read(PacketPtr pkt) default: panic("invalid access size!\n"); } - pkt->makeAtomicResponse(); } return pioDelay; } @@ -91,6 +91,7 @@ IsaFake::read(PacketPtr pkt) Tick IsaFake::write(PacketPtr pkt) { + pkt->makeAtomicResponse(); if (params()->warn_access != "") { uint64_t data; switch (pkt->getSize()) { @@ -138,7 +139,6 @@ IsaFake::write(PacketPtr pkt) panic("invalid access size!\n"); } } - pkt->makeAtomicResponse(); } return pioDelay; } diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index c502c5130..3434f59fb 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -119,17 +119,17 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt) DPRINTF(BusBridge, "Local queue size: %d outreq: %d outresp: %d\n", sendQueue.size(), queuedRequests, outstandingResponses); - DPRINTF(BusBridge, "Remove queue size: %d outreq: %d outresp: %d\n", + DPRINTF(BusBridge, "Remote queue size: %d outreq: %d outresp: %d\n", otherPort->sendQueue.size(), otherPort->queuedRequests, otherPort->outstandingResponses); - if (pkt->isRequest() && otherPort->reqQueueFull() && !pkt->wasNacked()) { + if (pkt->isRequest() && otherPort->reqQueueFull()) { DPRINTF(BusBridge, "Remote queue full, nacking\n"); nackRequest(pkt); return true; } - if (pkt->needsResponse() && !pkt->wasNacked()) + if (pkt->needsResponse()) if (respQueueFull()) { DPRINTF(BusBridge, "Local queue full, no space for response, nacking\n"); DPRINTF(BusBridge, "queue size: %d outreq: %d outstanding resp: %d\n", @@ -150,8 +150,8 @@ void Bridge::BridgePort::nackRequest(PacketPtr pkt) { // Nack the packet + pkt->makeTimingResponse(); pkt->setNacked(); - pkt->setDest(pkt->getSrc()); //put it on the list to send Tick readyTime = curTick + nackDelay; @@ -195,27 +195,23 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt) void Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) { - if (pkt->isResponse() || pkt->wasNacked()) { + if (pkt->isResponse()) { // This is a response for a request we forwarded earlier. The // corresponding PacketBuffer should be stored in the packet's // senderState field. + PacketBuffer *buf = dynamic_cast(pkt->senderState); assert(buf != NULL); // set up new packet dest & senderState based on values saved // from original request buf->fixResponse(pkt); - // Check if this packet was expecting a response and it's a nacked - // packet, in which case we will never being seeing it - if (buf->expectResponse && pkt->wasNacked()) - --outstandingResponses; - DPRINTF(BusBridge, "response, new dest %d\n", pkt->getDest()); delete buf; } - if (pkt->isRequest() && !pkt->wasNacked()) { + if (pkt->isRequest()) { ++queuedRequests; } @@ -249,7 +245,15 @@ Bridge::BridgePort::trySend() buf->origSrc, pkt->getDest(), pkt->getAddr()); bool wasReq = pkt->isRequest(); - bool wasNacked = pkt->wasNacked(); + bool was_nacked_here = buf->nackedHere; + + // If the send was successful, make sure sender state was set to NULL + // otherwise we could get a NACK back of a packet that didn't expect a + // response and we would try to use freed memory. + + Packet::SenderState *old_sender_state = pkt->senderState; + if (pkt->isRequest() && !buf->expectResponse) + pkt->senderState = NULL; if (sendTiming(pkt)) { // send successful @@ -266,12 +270,10 @@ Bridge::BridgePort::trySend() delete buf; } - if (!wasNacked) { - if (wasReq) - --queuedRequests; - else - --outstandingResponses; - } + if (wasReq) + --queuedRequests; + else if (!was_nacked_here) + --outstandingResponses; // If there are more packets to send, schedule event to try again. if (!sendQueue.empty()) { @@ -281,8 +283,10 @@ Bridge::BridgePort::trySend() } } else { DPRINTF(BusBridge, " unsuccessful\n"); + pkt->senderState = old_sender_state; inRetry = true; } + DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n", sendQueue.size(), queuedRequests, outstandingResponses); } diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index 82001948e..df48eb8c5 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -78,17 +78,19 @@ class Bridge : public MemObject public: Tick ready; PacketPtr pkt; + bool nackedHere; Packet::SenderState *origSenderState; short origSrc; bool expectResponse; PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false) - : ready(t), pkt(_pkt), - origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), + : ready(t), pkt(_pkt), nackedHere(nack), + origSenderState(_pkt->senderState), + origSrc(nack ? _pkt->getDest() : _pkt->getSrc() ), expectResponse(_pkt->needsResponse() && !nack) { - if (!pkt->isResponse() && !nack && !pkt->wasNacked()) + if (!pkt->isResponse() && !nack) pkt->senderState = this; } diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 620e2ac60..3f7b1deaf 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -237,6 +237,7 @@ Bus::recvTiming(PacketPtr pkt) if (dest_port_id == src) { // Must be forwarded snoop up from below... assert(dest == Packet::Broadcast); + assert(src != defaultId); // catch infinite loops } else { // send to actual target if (!dest_port->sendTiming(pkt)) { diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 02e951df4..f9a007c93 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -606,7 +606,13 @@ Cache::atomicAccess(PacketPtr pkt) DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n", busPkt->cmdString(), busPkt->getAddr(), old_state); - if (isCacheFill) { + bool is_error = busPkt->isError(); + assert(!busPkt->wasNacked()); + + if (is_error && pkt->needsResponse()) { + pkt->makeAtomicResponse(); + pkt->copyError(busPkt); + } else if (isCacheFill && !is_error) { PacketList writebacks; blk = handleFill(busPkt, blk, writebacks); satisfyCpuSideRequest(pkt, blk); @@ -667,6 +673,8 @@ Cache::handleResponse(PacketPtr pkt) { Tick time = curTick + hitLatency; MSHR *mshr = dynamic_cast(pkt->senderState); + bool is_error = pkt->isError(); + assert(mshr); if (pkt->wasNacked()) { @@ -675,7 +683,11 @@ Cache::handleResponse(PacketPtr pkt) "not implemented\n"); return; } - assert(!pkt->isError()); + if (is_error) { + DPRINTF(Cache, "Cache received packet with error for address %x, " + "cmd: %s\n", pkt->getAddr(), pkt->cmdString()); + } + DPRINTF(Cache, "Handling response to %x\n", pkt->getAddr()); MSHRQueue *mq = mshr->queue; @@ -702,7 +714,7 @@ Cache::handleResponse(PacketPtr pkt) miss_latency; } - if (mshr->isCacheFill) { + if (mshr->isCacheFill && !is_error) { DPRINTF(Cache, "Block for addr %x being updated in Cache\n", pkt->getAddr()); @@ -744,13 +756,18 @@ Cache::handleResponse(PacketPtr pkt) } else { // not a cache fill, just forwarding response completion_time = tags->getHitLatency() + pkt->finishTime; - if (pkt->isRead()) { + if (pkt->isRead() && !is_error) { target->pkt->setData(pkt->getPtr()); } } target->pkt->makeTimingResponse(); + // if this packet is an error copy that to the new packet + if (is_error) + target->pkt->copyError(pkt); cpuSidePort->respond(target->pkt, completion_time); } else { + // I don't believe that a snoop can be in an error state + assert(!is_error); // response to snoop request DPRINTF(Cache, "processing deferred snoop...\n"); handleSnoop(target->pkt, blk, true, true); diff --git a/src/mem/packet.cc b/src/mem/packet.cc index c7c6ec083..7b36be599 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -117,11 +117,11 @@ MemCmd::commandInfo[] = { SET5(IsRead, IsWrite, NeedsExclusive, IsResponse, HasData), InvalidCmd, "SwapResp" }, /* NetworkNackError -- nacked at network layer (not by protocol) */ - { SET2(IsRequest, IsError), InvalidCmd, "NetworkNackError" }, + { SET2(IsResponse, IsError), InvalidCmd, "NetworkNackError" }, /* InvalidDestError -- packet dest field invalid */ - { SET2(IsRequest, IsError), InvalidCmd, "InvalidDestError" }, + { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" }, /* BadAddressError -- memory address invalid */ - { SET2(IsRequest, IsError), InvalidCmd, "BadAddressError" } + { SET2(IsResponse, IsError), InvalidCmd, "BadAddressError" } }; diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 2b650a51e..9c366f9fc 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -332,10 +332,11 @@ class Packet : public FastAlloc // Network error conditions... encapsulate them as methods since // their encoding keeps changing (from result field to command // field, etc.) - void setNacked() { origCmd = cmd; cmd = MemCmd::NetworkNackError; } - void setBadAddress() { origCmd = cmd; cmd = MemCmd::BadAddressError; } + void setNacked() { assert(isResponse()); cmd = MemCmd::NetworkNackError; } + void setBadAddress() { assert(isResponse()); cmd = MemCmd::BadAddressError; } bool wasNacked() { return cmd == MemCmd::NetworkNackError; } bool hadBadAddress() { return cmd == MemCmd::BadAddressError; } + void copyError(Packet *pkt) { assert(pkt->isError()); cmd = pkt->cmd; } bool nic_pkt() { panic("Unimplemented"); M5_DUMMY_RETURN } @@ -431,6 +432,7 @@ class Packet : public FastAlloc { assert(needsResponse()); assert(isRequest()); + origCmd = cmd; cmd = cmd.responseCommand(); dest = src; destValid = srcValid;