From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 18:17:31 +0000 (-0800)
Subject: Print ".en=" only if there is an enable signal
X-Git-Tag: working-ls180~881^2^2~124^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=722eeacc095106a80bfda5326416a643af02738d;p=yosys.git

Print ".en=" only if there is an enable signal
---

diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc
index 7c3e52178..d914bcec0 100644
--- a/passes/hierarchy/clkpart.cc
+++ b/passes/hierarchy/clkpart.cc
@@ -262,7 +262,7 @@ struct ClkPartPass : public Pass {
 				auto en = std::get<3>(it.first);
 				std::string submod = stringf("clk=%s%s%s%s%s",
 						std::get<0>(it.first) ? "" : "!", clk.empty() ? "" : log_signal(clk),
-						std::get<2>(it.first) ? "" : "!", en.empty() ? ".en=" : "", en.empty() ? "" : log_signal(en));
+						std::get<2>(it.first) ? "" : "!", en.empty() ? "" : ".en=", en.empty() ? "" : log_signal(en));
 				for (auto c : it.second)
 					c->attributes[ID(submod)] = submod;
 				new_submods.push_back(stringf("%s_%s", mod->name.c_str(), submod.c_str()));