From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 20 Feb 2020 20:13:43 +0000 (+0000)
Subject: fix mask width
X-Git-Tag: partial-core-ls180-gdsii~231
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=723ef26418e629f81c1dd94d0c29e26da97dae3a;p=soclayout.git

fix mask width
---

diff --git a/examples/test_part_add.py b/examples/test_part_add.py
index 560db8d..2e1b234 100644
--- a/examples/test_part_add.py
+++ b/examples/test_part_add.py
@@ -20,13 +20,8 @@ class TestAddMod(Elaboratable):
         self.a = PartitionedSignal(partpoints, width)
         self.b = PartitionedSignal(partpoints, width)
         self.add_output = Signal(width)
-        self.le_output = Signal(len(partpoints)+1)
-        self.mux_sel = Signal(len(partpoints)+1)
-        self.mux_out = Signal(width)
         self.carry_in = Signal(len(partpoints)+1)
         self.add_carry_out = Signal(len(partpoints)+1)
-        self.sub_carry_out = Signal(len(partpoints)+1)
-        self.neg_output = Signal(width)
 
     def elaborate(self, platform):
         m = Module()
@@ -43,7 +38,7 @@ class TestAddMod(Elaboratable):
         return m
 if __name__ == '__main__':
     width = 16
-    pmask = Signal(4)  # divide into 4-bits
+    pmask = Signal(3)  # divide into 4-bits
     module = TestAddMod(width, pmask)
 
     create_ilang(module,