From: Kenneth Graunke Date: Wed, 30 Oct 2013 23:06:06 +0000 (-0700) Subject: i965: Fix brw_store_register_mem64 to stay within a single batch. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=723f047a3bc21b536d27ab1c0d6cc82f93002648;p=mesa.git i965: Fix brw_store_register_mem64 to stay within a single batch. Previously, the write of each 32-bit half might land in separate batch buffers, which is insane. Signed-off-by: Kenneth Graunke Reviewed-by: Chris Forbes --- diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index 56e9d5db937..5b469b5ddd0 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -112,14 +112,11 @@ brw_store_register_mem64(struct brw_context *brw, /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to * read a full 64-bit register, we need to do two of them. */ - BEGIN_BATCH(3); + BEGIN_BATCH(6); OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); OUT_BATCH(reg); OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, idx * sizeof(uint64_t)); - ADVANCE_BATCH(); - - BEGIN_BATCH(3); OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); OUT_BATCH(reg + sizeof(uint32_t)); OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,