From: Luke Kenneth Casson Leighton Date: Mon, 6 Jul 2020 13:10:59 +0000 (+0100) Subject: add mtmsr internal op X-Git-Tag: div_pipeline~162^2~36 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72553d725b79050a9cf92de710ac67a914c39525;p=soc.git add mtmsr internal op --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 79e40ec5..45b60fb9 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -44,6 +44,7 @@ def instr_is_priv(m, op, insn): with m.Case(InternalOp.OP_ATTN) : comb += is_priv_insn.eq(1) with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1) with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1) + with m.Case(InternalOp.OP_MTMSR): comb += is_priv_insn.eq(1) with m.Case(InternalOp.OP_RFID) : comb += is_priv_insn.eq(1) with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1) with m.If(op == OP_MFSPR | op == OP_MTSPR):