From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 Dec 2021 15:16:30 +0000 (+0000)
Subject: remove update of pc, msr and svstate from TestIssuerInOrder
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=726075686838fdf786907740dc0802ecd51c32bb;p=soc.git

remove update of pc, msr and svstate from TestIssuerInOrder
---

diff --git a/src/soc/simple/inorder.py b/src/soc/simple/inorder.py
index b930ecb9..3916ad42 100644
--- a/src/soc/simple/inorder.py
+++ b/src/soc/simple/inorder.py
@@ -275,15 +275,6 @@ class TestIssuerInternalInOrder(TestIssuerBase):
                 with m.Else():
                     # tell core it's stopped, and acknowledge debug handshake
                     comb += dbg.core_stopped_i.eq(1)
-                    # while stopped, allow updating the MSR, PC and SVSTATE
-                    with m.If(self.pc_i.ok):
-                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
-                        comb += self.state_w_pc.i_data.eq(self.pc_i.data)
-                        sync += self.pc_changed.eq(1)
-                    with m.If(self.msr_i.ok):
-                        comb += self.state_w_msr.wen.eq(1 << StateRegs.MSR)
-                        comb += self.state_w_msr.i_data.eq(self.msr_i.data)
-                        sync += self.msr_changed.eq(1)
 
             # wait for an instruction to arrive from Fetch
             with m.State("INSN_WAIT"):