From: lkcl <lkcl@web>
Date: Thu, 5 May 2022 23:10:37 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2411
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=726c4b581b3938c5cee87aefedb2c1caa303643d;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 347a95c15..f6c88389f 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -30,7 +30,8 @@ significant apparent speed increases: 3200 mhz DDR4 and even faster DDR5,
 and other advanced Memory interfaces such as HBM, Gen-Z, and OpenCAPI,
 all make an effort (all simply increasing the parallel deployment of
 the underlying 150 mhz bitcells), but these efforts are dwarfed by the
-two nearly three orders of magnitude increase in CPU horsepower. Seymour
+two nearly three orders of magnitude increase in CPU horsepower
+over the same timeframe. Seymour
 Cray, from his amazing in-depth knowledge, predicted that the mismatch
 would become a serious limitation, over two decades ago.  Some systems
 at the time of writing are now approaching a *Gigabyte* of L4 Cache,