From: Tim Newsome <tim@sifive.com>
Date: Tue, 21 Jun 2016 00:38:20 +0000 (-0700)
Subject: Make DownloadTest pass on boards with little RAM.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72822ba60b710dc2ce0c9cffbc990d99e93490c1;p=riscv-tests.git

Make DownloadTest pass on boards with little RAM.
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 027d387..deb3d57 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -354,7 +354,7 @@ class RegsTest(DeleteServer):
 
 class DownloadTest(DeleteServer):
     def setUp(self):
-        length = 2**20
+        length = min(2**20, target.ram_size - 2048)
         fd = file("download.c", "w")
         fd.write("#include <stdint.h>\n")
         fd.write("unsigned int crc32a(uint8_t *message, unsigned int size);\n")
@@ -423,6 +423,7 @@ class Spike64Target(Target):
     name = "spike"
     xlen = 64
     ram = 0x80010000
+    ram_size = 5 * 1024 * 1024
 
     def server(self):
         return testlib.Spike(parsed.cmd, halted=True)
@@ -432,6 +433,7 @@ class Spike32Target(Target):
     directory = "spike"
     xlen = 32
     ram = 0x80010000
+    ram_size = 5 * 1024 * 1024
 
     def server(self):
         return testlib.Spike(parsed.cmd, halted=True, xlen=32)
@@ -440,6 +442,7 @@ class MicroSemiTarget(Target):
     name = "m2gl_m2s"
     xlen = 32
     ram = 0x80000000
+    ram_size = 16 * 1024
 
     def server(self):
         return testlib.Openocd(cmd=parsed.cmd,