From: lkcl <lkcl@web>
Date: Wed, 14 Sep 2022 16:33:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~449
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7288638fca0074e673d34fe40b011c2058bc4201;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 3d1eff299..483862f87 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -224,6 +224,21 @@ The primary options are:
   elements may be excluded from outputting to the regfile then
   post-analysed outside of critical hot-loops.
 
+**RM Modes**
+
+There are five primary categories of instructions in Power ISA, each of
+which needed slightly different Modes. For example, saturation and
+element-width overrides are meaningless to Condition Register Field
+operations, and Reduction is meaningless to LD/ST but Saturation
+saves register file ports in critical hot-loops. Thus the 24 bits may
+be suitably adapted to each category.
+
+* Normal - arithmetic and logical including IEEE754 FP
+* LD/ST immediate - includes element-strided and unit-strided
+* LD/ST indexed
+* CR Field ops
+* Branch-Conditional - saves on instruction count in 3D parallel if/else
+
 **SVP64Single**
 
 The `SVP64-Single` 24-bit encoding focusses primarily on ensuring that