From: Andrew Waterman Date: Wed, 11 Sep 2013 11:12:05 +0000 (-0700) Subject: Add AMOXOR test X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=728924ea6db6f6c3ee11554c3ad79d9bdabbe57e;p=riscv-tests.git Add AMOXOR test --- diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag index b3799bc..adb015a 100644 --- a/isa/rv64ui/Makefrag +++ b/isa/rv64ui/Makefrag @@ -4,8 +4,8 @@ rv64ui_sc_tests = \ add addi addiw addw \ - amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoswap_d \ - amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \ + amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ and andi \ auipc \ beq bge bgeu blt bltu bne \ diff --git a/isa/rv64ui/amoxor_d.S b/isa/rv64ui/amoxor_d.S new file mode 100644 index 0000000..81ebe00 --- /dev/null +++ b/isa/rv64ui/amoxor_d.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# amoxor_d.S +#----------------------------------------------------------------------------- +# +# Test amoxor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ui/amoxor_w.S b/isa/rv64ui/amoxor_w.S new file mode 100644 index 0000000..79579d2 --- /dev/null +++ b/isa/rv64ui/amoxor_w.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xc0000001; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536