From: Kyrylo Tkachov Date: Fri, 24 Apr 2015 15:01:32 +0000 (+0000) Subject: [ARM][trivial] Use uppercase for code iterator names X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=728dc15380585e6706357092c0b7becfc48f5133;p=gcc.git [ARM][trivial] Use uppercase for code iterator names * config/arm/iterators.md (shiftable_ops): Rename to... (SHIFTABLE_OPS): ... This. Update use in comments. (ior_xor): Rename to... (IOR_XOR): ... This. (vqh_ops): Rename to... (VQH_OPS): ... This. (vqhs_ops): Rename to... (VQHS_OPS): ... This. (rshifts): Rename to... (RSHIFTS): ... This. (returns): Rename to... (RETURNS): ... This. * config/arm/arm.md: Update uses of the above. * config/arm/neon.md: Likewise. From-SVN: r222416 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f29024a7e1e..9f7036f2392 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2015-04-24 Kyrylo Tkachov + + * config/arm/iterators.md (shiftable_ops): Rename to... + (SHIFTABLE_OPS): ... This. Update use in comments. + (ior_xor): Rename to... + (IOR_XOR): ... This. + (vqh_ops): Rename to... + (VQH_OPS): ... This. + (vqhs_ops): Rename to... + (VQHS_OPS): ... This. + (rshifts): Rename to... + (RSHIFTS): ... This. + (returns): Rename to... + (RETURNS): ... This. + * config/arm/arm.md: Update uses of the above. + * config/arm/neon.md: Likewise. + 2014-04-24 Kyrylo Tkachov * config.host (case ${host}): Add aarch64*-*-linux case. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 1b5e62ec517..85d27d93a58 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5076,7 +5076,7 @@ (define_split [(set (match_operand:SI 0 "s_register_operand" "") - (ior_xor:SI (and:SI (ashift:SI + (IOR_XOR:SI (and:SI (ashift:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "const_int_operand" "")) (match_operand:SI 3 "const_int_operand" "")) @@ -5088,7 +5088,7 @@ == (GET_MODE_MASK (GET_MODE (operands[5])) & (GET_MODE_MASK (GET_MODE (operands[5])) << (INTVAL (operands[2])))))" - [(set (match_dup 0) (ior_xor:SI (ashift:SI (match_dup 1) (match_dup 2)) + [(set (match_dup 0) (IOR_XOR:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 4))) (set (match_dup 0) (zero_extend:SI (match_dup 5)))] "operands[5] = gen_lowpart (GET_MODE (operands[5]), operands[0]);" @@ -7848,7 +7848,7 @@ ) (define_expand "return" - [(returns)] + [(RETURNS)] "(TARGET_ARM || (TARGET_THUMB2 && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL && !IS_STACKALIGN (arm_current_func_type ()))) @@ -7886,7 +7886,7 @@ [(set (pc) (if_then_else (match_operator 0 "arm_comparison_operator" [(match_operand 1 "cc_register" "") (const_int 0)]) - (returns) + (RETURNS) (pc)))] "TARGET_ARM " "* @@ -7909,7 +7909,7 @@ (if_then_else (match_operator 0 "arm_comparison_operator" [(match_operand 1 "cc_register" "") (const_int 0)]) (pc) - (returns)))] + (RETURNS)))] "TARGET_ARM " "* { @@ -8243,7 +8243,7 @@ (define_insn "*_multsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (shiftable_ops:SI + (SHIFTABLE_OPS:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "power_of_two_operand" "")) (match_operand:SI 1 "s_register_operand" "rk,")))] @@ -8257,7 +8257,7 @@ (define_insn "*_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (shiftable_ops:SI + (SHIFTABLE_OPS:SI (match_operator:SI 2 "shift_nomul_operator" [(match_operand:SI 3 "s_register_operand" "r,r,r") (match_operand:SI 4 "shift_amount_operand" "M,M,r")]) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 66f3f4d7d9f..1e7f3f17a8a 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -191,34 +191,34 @@ (define_code_iterator COMPARISONS [eq gt ge le lt]) ;; A list of ... -(define_code_iterator ior_xor [ior xor]) +(define_code_iterator IOR_XOR [ior xor]) ;; Operations on two halves of a quadword vector. -(define_code_iterator vqh_ops [plus smin smax umin umax]) +(define_code_iterator VQH_OPS [plus smin smax umin umax]) ;; Operations on two halves of a quadword vector, ;; without unsigned variants (for use with *SFmode pattern). -(define_code_iterator vqhs_ops [plus smin smax]) +(define_code_iterator VQHS_OPS [plus smin smax]) ;; A list of widening operators (define_code_iterator SE [sign_extend zero_extend]) ;; Right shifts -(define_code_iterator rshifts [ashiftrt lshiftrt]) +(define_code_iterator RSHIFTS [ashiftrt lshiftrt]) ;; Iterator for integer conversions (define_code_iterator FIXUORS [fix unsigned_fix]) ;; Binary operators whose second operand can be shifted. -(define_code_iterator shiftable_ops [plus minus ior xor and]) +(define_code_iterator SHIFTABLE_OPS [plus minus ior xor and]) -;; plus and minus are the only shiftable_ops for which Thumb2 allows +;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows ;; a stack pointer opoerand. The minus operation is a candidate for an rsub ;; and hence only plus is supported. (define_code_attr t2_binop0 [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) -;; The instruction to use when a shiftable_ops has a shift operation as +;; The instruction to use when a SHIFTABLE_OPS has a shift operation as ;; its first operand. (define_code_attr arith_shift_insn [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) @@ -797,7 +797,7 @@ (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) ;; Both kinds of return insn. -(define_code_iterator returns [return simple_return]) +(define_code_iterator RETURNS [return simple_return]) (define_code_attr return_str [(return "") (simple_return "simple_")]) (define_code_attr return_simple_p [(return "false") (simple_return "true")]) (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 445df2ad0bd..a48c39ba118 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1114,7 +1114,7 @@ ;; lshrdi3_neon (define_insn_and_split "di3_neon" [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?w,?w") - (rshifts:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w") + (RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w") (match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, r, i"))) (clobber (match_scratch:SI 3 "=2r, X, &r, X,2r, X")) (clobber (match_scratch:SI 4 "= X, X, &r, X, X, X")) @@ -1267,7 +1267,7 @@ (define_insn "quad_halves_v4si" [(set (match_operand:V2SI 0 "s_register_operand" "=w") - (vqh_ops:V2SI + (VQH_OPS:V2SI (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") (parallel [(const_int 0) (const_int 1)])) (vec_select:V2SI (match_dup 1) @@ -1280,7 +1280,7 @@ (define_insn "quad_halves_v4sf" [(set (match_operand:V2SF 0 "s_register_operand" "=w") - (vqhs_ops:V2SF + (VQHS_OPS:V2SF (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") (parallel [(const_int 0) (const_int 1)])) (vec_select:V2SF (match_dup 1) @@ -1293,7 +1293,7 @@ (define_insn "quad_halves_v8hi" [(set (match_operand:V4HI 0 "s_register_operand" "+w") - (vqh_ops:V4HI + (VQH_OPS:V4HI (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])) @@ -1308,7 +1308,7 @@ (define_insn "quad_halves_v16qi" [(set (match_operand:V8QI 0 "s_register_operand" "+w") - (vqh_ops:V8QI + (VQH_OPS:V8QI (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)