From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 13:33:40 +0000 (+0100)
Subject: add category descriptions
X-Git-Tag: convert-csv-opcode-to-binary~4947
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7292da748c7e074f75655457e7a6e85189578331;p=libreriscv.git

add category descriptions
---

diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn
index 157be7828..478eeb778 100644
--- a/simple_v_extension/opcodes.mdwn
+++ b/simple_v_extension/opcodes.mdwn
@@ -4,7 +4,7 @@ Based on information from Michael Clark's riscv-meta opcodes table, this
 page categorises and identifies the type of parallelism that SimpleV
 indirectly adds on each RISC-V **standard** opcode.
 
-* **-** - no action
+* **-** no action
 * **sv** - a standard contiguous (optionally predicated, optionally
   indirected) multi-register operation where the predication for
   the operation is taken from the **destination** register