From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 12:11:09 +0000 (+0100)
Subject: add set only first demo
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72989dd9f956de578634355da0b5b6b21696b85e;p=libreriscv.git

add set only first demo
---

diff --git a/openpower/sv/sof.py b/openpower/sv/sof.py
new file mode 100644
index 000000000..164c32623
--- /dev/null
+++ b/openpower/sv/sof.py
@@ -0,0 +1,39 @@
+def sof(RA, mask=None, zero=False):
+    RT = RA if mask is not None and not zero else 0
+    i = 0
+    # start setting if no predicate or if 1st predicate bit set
+    setting_mode = mask is None
+    found = False
+    while i < 16:
+        bit = 1<<i
+        if not setting_mode and mask is not None and (mask & bit):
+            setting_mode = True # back into "setting" mode
+            found = False
+        if setting_mode:
+            if mask is not None and not (mask & bit):
+                setting_mode = False
+            elif RA & bit: # found a bit in rs1: stop setting RT
+                if not found:
+                    found = True
+                    RT |= bit
+        i += 1
+    return RT
+
+if __name__ == '__main__':
+     m  = 0b11000011
+     v3 = 0b10010100 # vmsof.m v2, v3
+     v2 = 0b01000000 # v2
+     RT = sof(v3, m, True)
+     print(bin(v3), bin(v2), bin(RT))
+     v3 = 0b10010100 # vmsof.m v2, v3
+     v2 = 0b00000100 # v2 contents
+     RT = sof(v3)
+     print(bin(v3), bin(v2), bin(RT))
+     v3 = 0b10010101 # vmsof.m v2, v3
+     v2 = 0b00000001 # v2
+     RT = sof(v3)
+     print(bin(v3), bin(v2), bin(RT))
+     v3 = 0b00000000 # vmsof.m v2, v3
+     v2 = 0b00000000 # v2
+     RT = sof(v3)
+     print(bin(v3), bin(v2), bin(RT))