From: Udi Finkelstein <github@udifink.com>
Date: Sat, 30 Sep 2017 03:39:07 +0000 (+0300)
Subject: Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
X-Git-Tag: yosys-0.8~306^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72a08eca3dd6e7df1094c83afb97a0a293a1117e;p=yosys.git

Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
(Oreilly 'Flex & Bison' page 189)
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 9fa2a1a2f..ec92f6628 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -142,7 +142,9 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %define parse.error verbose
 %define parse.lac full
 
-%expect 2
+%nonassoc FAKE_THEN
+%nonassoc TOK_ELSE
+
 %debug
 
 %%
@@ -1261,7 +1263,7 @@ optional_else:
 		ast_stack.back()->children.push_back(cond);
 		ast_stack.push_back(block);
 	} behavioral_stmt |
-	/* empty */;
+	/* empty */ %prec FAKE_THEN;
 
 case_body:
 	case_body case_item |
@@ -1432,7 +1434,7 @@ gen_stmt_or_null:
 	gen_stmt_block | ';';
 
 opt_gen_else:
-	TOK_ELSE gen_stmt_or_null | /* empty */;
+	TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
 
 expr:
 	basic_expr {