From: lkcl <lkcl@web>
Date: Sun, 1 Aug 2021 21:51:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~549
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72ae2c4263b9f94f896678e8b58ef0890592cd38;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index eab4c99ba..982545e64 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -223,7 +223,7 @@ than the normal 0..VL-1
 * **N** sets signed/unsigned saturation.
 **RC1** as if Rc=1, stores CRs *but not the result*
 
-For LD/ST Modes, see [[sv/ldst]].  For Branch modes, see [[sv/branch]] Immediate and Indexed LD/ST
+For LD/ST Modes, see [[sv/ldst]].  For Branch modes, see [[sv/branches]] Immediate and Indexed LD/ST
 are both different, in order to support a large range of features
 normally found in Vector ISAs.