From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 14 Nov 2018 21:55:40 +0000 (+0000)
Subject: comment out debug code not needed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72afe07787794f972ad5af84d17bba0ee4852886;p=riscv-isa-sim.git

comment out debug code not needed
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index d235ce3..64f9fe7 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -129,15 +129,14 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
 #endif
   }
-  // identify which regs have had their CSR entries set as vectorised.
-  // really could do with a macro for-loop here... oh well...
-  // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
+#if 0 // useful test at one point...
   if (insn.sv_check_reg(true, 15))
   {
     fprintf(stderr, "reg %s %x rd %ld rs1 %ld rs2 %ld vlen %d\n",
             xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
             vlen);
   }
+#endif
   // if vectorop is set, one of the regs is not a scalar,
   // so we must read the VL CSR and do a loop
   if (vlen == 0)