From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Nov 2013 13:10:46 +0000 (+0100)
Subject: Fixed "flatten" top-module detection: Only use on fully selected designs
X-Git-Tag: yosys-0.2.0~319
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72b35e0b99381df7bda7fdd2811e67ae5cfad80a;p=yosys.git

Fixed "flatten" top-module detection: Only use on fully selected designs
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 7e3ba23ec..4f9d9c4e4 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -501,9 +501,10 @@ struct FlattenPass : public Pass {
 			celltypeMap[it.first].insert(it.first);
 
 		RTLIL::Module *top_mod = NULL;
-		for (auto &mod_it : design->modules)
-			if (mod_it.second->get_bool_attribute("\\top"))
-				top_mod = mod_it.second;
+		if (design->full_selection())
+			for (auto &mod_it : design->modules)
+				if (mod_it.second->get_bool_attribute("\\top"))
+					top_mod = mod_it.second;
 
 		bool did_something = true;
 		std::set<RTLIL::Cell*> handled_cells;