From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Mar 2011 06:42:18 +0000 (-0800)
Subject: X86: Mark prefetches as such in their instruction and request flags.
X-Git-Tag: stable_2012_02_02~504
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72d35701e9842a454ea0bd1e4546d161c3024f93;p=gem5.git

X86: Mark prefetches as such in their instruction and request flags.
---

diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index cd649d644..86c2dccf7 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -282,8 +282,10 @@ let {{
             self.memFlags = baseFlags
             if atCPL0:
                 self.memFlags += " | (CPL0FlagBit << FlagShift)"
+            self.instFlags = ""
             if prefetch:
                 self.memFlags += " | Request::PREFETCH"
+                self.instFlags += " | StaticInst::IsDataPrefetch"
             self.memFlags += " | (machInst.legacy.addr ? " + \
                              "(AddrSizeFlagBit << FlagShift) : 0)"
 
@@ -293,7 +295,7 @@ let {{
                     %(disp)s, %(segment)s, %(data)s,
                     %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
                 "class_name" : self.className,
-                "flags" : self.microFlagsText(microFlags),
+                "flags" : self.microFlagsText(microFlags) + self.instFlags,
                 "scale" : self.scale, "index" : self.index,
                 "base" : self.base,
                 "disp" : self.disp,