From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 May 2023 18:28:27 +0000 (+0100)
Subject: fix data-dependent fail-first on load
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72d3f047346c22ccb79fadbe406af15b4f3bb993;p=openpower-isa.git

fix data-dependent fail-first on load
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index f0c43bc1..0807e47a 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2227,11 +2227,13 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             self.crl[regnum].eq(cr0)
 
     def do_outregs_nia(self, asmop, ins_name, info, outs,
-                       carry_en, rc_en, ffirst_hit, ew_dst):
+                       ca_en, rc_en, ffirst_hit, ew_dst):
         ffirst_hit, vli = ffirst_hit
-        # write out any regs for this instruction
-        for name, output in outs.items():
-            yield from self.check_write(info, name, output, carry_en, ew_dst)
+        # write out any regs for this instruction, but only if fail-first is ok
+        # XXX TODO: allow CR-vector to be written out even if ffirst fails
+        if not ffirst_hit or vli:
+            for name, output in outs.items():
+                yield from self.check_write(info, name, output, ca_en, ew_dst)
         # restore the CR value on non-VLI failfirst (from sv.cmp and others
         # which write directly to CR in the pseudocode (gah, what a mess)
         # if ffirst_hit and not vli:
diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
index f4b7d226..58acee8f 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
@@ -709,7 +709,7 @@ class DecoderTestCase(FHDLTestCase):
         lst = SVP64Asm(
             [
                 # load VL bytes but test if they are zero and truncate
-                "sv.lbz/ff=RC1 *16, 1(10)",
+                "sv.lbz/ff=RC1 *16, 1(10)", # deliberately offset by 1
             ]
         )
         lst = list(lst)
@@ -728,6 +728,13 @@ class DecoderTestCase(FHDLTestCase):
         for i in range(8): # set to garbage
             initial_regs[16+i] = (0xbeef00) + i  # identifying garbage
 
+        # calculate expected regs
+        expected_regs = deepcopy(initial_regs)
+        for i, c in enumerate(tst_string[1:]): # note the offset 1(10)
+            c = ord(c)
+            if c == 0: break # strcpy stop at NUL
+            expected_regs[16+i] = c
+
         # some memory with identifying garbage in it
         initial_mem = {16: 0xf0f1_f2f3_f4f5_f6f7,
                        24: 0x4041_4243_4445_4647,
@@ -744,7 +751,10 @@ class DecoderTestCase(FHDLTestCase):
                                        initial_regs=initial_regs)
             mem = sim.mem.dump(printout=True, asciidump=True)
             print (mem)
-            self.assertEqual(sim.svstate.vl, 1)
+            self.assertEqual(sim.svstate.vl, 2)
+            for i in range(len(expected_regs)):
+                print ("%i %x %x" % (i, sim.gpr(i).value, expected_regs[i]))
+                self.assertEqual(sim.gpr(i), expected_regs[i])
 
     def run_tst_program(self, prog, initial_regs=None,
                         svstate=None, initial_fprs=None,