From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Mar 2022 12:21:48 +0000 (+0100)
Subject: try latency of 7 for winbond hyperram
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72df4d856773f0485b5bee3ec0b2bf1ef6616dd3;p=ls2.git

try latency of 7 for winbond hyperram
---

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 044283b..8000d05 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -60,29 +60,29 @@ void isr(void) {
 
 int main(void) {
 	const int kNumIterations = 14;
-	int res, failcnt = 0;
+	int res, failcnt = 0, i=0;
 	uint32_t tmp;
 	volatile uint32_t *ram = (uint32_t*)DRAM_BASE;
 	console_init();
 	//puts("Firmware launched...\n");
 
-	//puts("fw..");
+	puts("fw..");
 #if 1
 	volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
     writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
     tmp = readl((unsigned long)&(hyperram[0]));
-    return 0;
     while (1) {
         unsigned char c = getchar();
         putchar(c);
         if (c == 13) { // if CR send LF
 
             // quick write/read
-            writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
+            writel(0xDEAF0123+i, (unsigned long)&(hyperram[0]));
             tmp = readl((unsigned long)&(hyperram[0]));
             puts("read ");
             uart_writeuint32(tmp);
             putchar(10);
+            i++;
         }
     }
 
diff --git a/src/ls2.py b/src/ls2.py
index 1a2bd29..688fea1 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -416,7 +416,8 @@ class DDR3SoC(SoC, Elaboratable):
         # moment
         if hyperram_pins is not None:
             self.hyperram = HyperRAM(io=hyperram_pins, phy_kls=HyperRAMPHY,
-                                     features={'stall'})
+                                     features={'stall'},
+                                     latency=7) # Winbond W956D8MBYA
             self._decoder.add(self.hyperram.bus, addr=hyperram_addr)
 
         self.memory_map = self._decoder.bus.memory_map
@@ -483,7 +484,6 @@ class DDR3SoC(SoC, Elaboratable):
             comb += hyperram.bus.stall.eq(hyperram.bus.cyc & ~hyperram.bus.ack)
             # set 3 top CSn lines to zero for now
             if self.fpga == 'arty_a7':
-                comb += hyperram.phy.cs[1:].eq(Const(0, 3))
                 comb += hyperram.phy.rst_n.eq(1)
 
         # add blinky lights so we know FPGA is alive