From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Jan 2020 00:49:34 +0000 (-0800)
Subject: Explicitly create separate $mux cells
X-Git-Tag: working-ls180~819^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72e4540ca9749a0b7621e91e32e5aabf24b29b74;p=yosys.git

Explicitly create separate $mux cells
---

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 95cfa66b2..75a51e55e 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -151,13 +151,13 @@ module _90_shift_shiftx (A, B, Y);
 			//   the LSB of B, after discarding the zeroed bits
 			localparam len = 2**(B_WIDTH-1);
 			localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
-			wire [len-1:0] T, F;
+			wire [len-1:0] T, F, AA;
 			genvar i;
 			for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
 				assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
 				assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}};
+				assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2];
 			end
-			wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F;
 			wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
 			if (_TECHMAP_CELLTYPE_ == "$shift")
 				$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));