From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 16 Aug 2019 11:21:11 +0000 (+0200)
Subject: Regression in abc9
X-Git-Tag: working-ls180~1139^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72eacdb9f80e24aa2182dbf567d6fcbe2a5bfaba;p=yosys.git

Regression in abc9
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 752535f34..c3c8f879f 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -628,7 +628,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 				if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
 				continue;
 			}
-			cell_stats[RTLIL::unescape_id(c->type)]++;
+			cell_stats[c->type]++;
 
 			RTLIL::Cell *existing_cell = nullptr;
 			if (c->type == ID($lut)) {