From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 16 Apr 2021 00:43:28 +0000 (+0100)
Subject: corrections to wishbone test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72f72bbc57b852a38b71eb2c8ba90f98ecb956e9;p=soc-cocotb-sim.git

corrections to wishbone test
---

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 2c1174d..718faf5 100644
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -216,7 +216,7 @@ def wishbone_basic(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    #assert master.result.binstr == "000000000000000000000000000010"
+    assert master.result.binstr == "000000000000000000000000000011"
 
     # Do read
     yield master.load_ir(cmd_MEMREAD)
@@ -241,7 +241,7 @@ def wishbone_basic(dut):
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "000000000000000000000000000010"
+    assert master.result.binstr == "000000000000000000000000000011"
 
     # Do read
     yield master.load_ir(cmd_MEMREAD) # MEMREAD