From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 29 Apr 2021 22:00:52 +0000 (+0100)
Subject: comment out adding mmu and dcache to pspec in MMU FSM
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=72f7b42941ca1c1c68dbff0c474e38a62fe7b11f;p=soc.git

comment out adding mmu and dcache to pspec in MMU FSM
---

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index a6e485ac..6b72c8a2 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -164,9 +164,12 @@ class FSMMMUStage(ControlBase):
 
         self.mmu = MMU()
 
-        # make life a bit easier in Core
-        self.pspec.mmu = self.mmu
-        self.pspec.dcache = self.dcache
+        # make life a bit easier in Core XXX mustn't really do this,
+        # pspec is designed for config variables, rather than passing
+        # things around.  have to think about it, design a way to do
+        # it that makes "sense"
+        # comment out for now self.pspec.mmu = self.mmu
+        # comment out for now self.pspec.dcache = self.dcache
 
         # debugging output for gtkw
         self.debug0 = Signal(4)