From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Jan 2022 17:46:56 +0000 (+0000)
Subject: fix MMU lookup after 2nd request (misaligned) by also updating the
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=731a5d08f26ee331b5b9f5399985105aa50e370e;p=soc.git

fix MMU lookup after 2nd request (misaligned) by also updating the
ldst_r with the next address/byte_sel
---

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index 13a6909a..a21a4e08 100644
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -921,7 +921,7 @@ def test_loadstore1_microwatt_mmu_bin_test5():
 
     m, cmpi = setup_mmu()
 
-    mem = pagetables.microwatt_test2
+    mem = pagetables.microwatt_test5
 
     # nmigen Simulation
     sim = Simulator(m)
diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index ce77353a..36836c67 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -306,6 +306,8 @@ class LoadStore1(PortInterfaceBase):
                         comb += self.req.raddr.eq(ldst_r.raddr + 8)
                         comb += self.req.byte_sel.eq(ldst_r.byte_sel[8:])
                         comb += self.req.alignstate.eq(Misalign.WAITSECOND)
+                        sync += ldst_r.raddr.eq(ldst_r.raddr + 8)
+                        sync += ldst_r.byte_sel.eq(ldst_r.byte_sel[8:])
                         sync += ldst_r.alignstate.eq(Misalign.WAITSECOND)
                         sync += Display("    second req %x", self.req.raddr)
                     with m.Elif(ldst_r.alignstate == Misalign.WAITSECOND):