From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Apr 2019 16:08:19 +0000 (+0100)
Subject: do flatten on output data
X-Git-Tag: ls180-24jan2020~1256
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=732e64ce8ae050c6f721223dc3156175becd72f2;p=ieee754fpu.git

do flatten on output data
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index e8d16ef5..1a31d078 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -1042,19 +1042,17 @@ class FIFOtest(ControlBase):
         fifo = SyncFIFO(fwidth, self.fdepth)
         m.submodules.fifo = fifo
 
-        # connect the rdy/valid/data
+        # connect previous rdy/valid/data - do flatten on i_data
         m.d.comb += [fifo.we.eq(self.p.i_valid_test),
                      self.p.o_ready.eq(fifo.writable),
                      eq(fifo.din, flatten(self.p.i_data)),
                    ]
 
-        # next: make the FIFO "look" like a NextControl...
-        fn = NextControl()
-        fn.o_valid = fifo.readable
-        fn.i_ready = fifo.re
-        fn.o_data = fifo.dout
-        # ... so we can do this!
-        m.d.comb += fn._connect_out(self.n)
+        # connect next rdy/valid/data - do flatten on o_data
+        m.d.comb += [self.n.o_valid.eq(fifo.readable),
+                     fifo.re.eq(self.n.i_ready_test),
+                     flatten(self.n.o_data).eq(fifo.dout),
+                   ]
 
         # err... that should be all!
         return m